Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Katsuyoshi Mitsui is active.

Publication


Featured researches published by Katsuyoshi Mitsui.


IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | 1994

Reverse short-channel effect due to lateral diffusion of point-defect induced by source/drain ion implantation

Tatsuya Kunikiyo; Katsuyoshi Mitsui; Masato Fujinaga; T. Uchida; Norihiko Kotani

Presents a physical model of reverse short-channel effects on threshold voltage caused by lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by ion implantation in source/drain region of n-channel MOS devices. Based on the process and device simulation, it is shown that lateral diffusion of the Frenkel pairs enhances diffusion of channel dopant, and results in nonuniform lateral distribution. This phenomenon causes the threshold voltage increase in the short-channel devices. The authors extracted parameters on point-defect diffusion from the comparison of calculated results with experimental data on threshold voltage. Calculated arsenic profile in the source/drain region using those parameters shows good agreement with the experimental data measured by secondary ion mass spectroscopy (SIMS). The close agreement between simulation and experimental results both on the arsenic profile in source/drain region and threshold voltage confirms the validity of the model and extracted parameters. >


international electron devices meeting | 1991

Gate capacitance characteristics of gate N/sup -/ overlap LDD transistor with high performance and high reliability

Masahide Inuishi; Katsuyoshi Mitsui; Shigeru Kusunoki; Hidekazu Oda; Katsuhiro Tsukamoto; Y. Akasaka

The authors present the gate capacitance characteristics of the gate/N/sup -/ overlap LDD (lightly doped drain) transistor. The gate capacitance was directly measured by a four-terminal method, using an LCR meter. The measured results for the overlap LDD were compared with those for the single drain and the LDD structure. It was demonstrated that the gate/drain capacitance for the overlap LDD is smaller than that for the single drain and as small as that for the LDD in spite of the large overlap length between the gate and the N/sup -/ region. This result was also confirmed by simulation, which indicates that the small gate/drain capacitance of the overlap LDD is due to the depletion of the N/sup -/ drain under the gate by the normal electric field from the gate and the lateral electric field at the drain.<<ETX>>


NUPAD IV. Workshop on Numerical Modeling of Processes and Devices for Integrated Circuits, | 1992

Reverse Short-Channel Effects due to the Lateral Diffusion of the Point-Defects Induced by the Source/Drain Ion Implantation

T. Kunikiyo; Katsuyoshi Mitsui; Masato Fujinaga; Tetsuya Uchida; Norihiko Kotani; Yoichi Akasaka

A physical model of reverse short-channel effect on the threshold voltage caused by the lateral diffusion of the Frenkel pairs (interstitial-vacancy) induced by tlie ion implantation in the source/drain region is presented. Based on the process and device simulation, it is shown that the lateral diffusion of the Frenkel pairs enhances the diffusion of the channel dopant, which results in the nonuniform lateral distribution of the channel dopant and in the increase in the threshold voltage as the channel length is reduced.


international electron devices meeting | 1989

A high performance and highly reliable dual gate CMOS with gate/n/sup -/ overlapped LDD applicable to the cryogenic operation

Masahide Inuishi; Katsuyoshi Mitsui; Shigeru Kusunoki; Masahiro Shimizu; Katsuhiro Tsukamoto

A dual-gate CMOS structure has been developed which features an overlap LDD (lightly doped drain) NMOS with n/sup +/ poly gate and a surface channel PMOS with p/sup +/ poly gate whose source/drain and gate were salicided with low-resistance TiSi/sub 2/. The gate/n/sup -/ overlapped structure was fabricated by rotational oblique ion implantation. This CMOS structure can realize low-supply-voltage operation due to the small absolute value of threshold voltage without punchthrough. It is demonstrated that, using the overlap LDD NMOS, the circuit speed and the reliability can be improved, compared with the single and the conventional LDD NMOS. The cryogenic operation of the structure is examined.<<ETX>>


Archive | 1991

Method of fabricating semiconductor device having sidewall spacers and oblique implantation

Masahiro Shimizu; Katsuyoshi Mitsui; Yomiyuki Yama; Masatoshi Yasunaga


Archive | 1990

Mis semiconductor device

Katsuyoshi Mitsui; Masahide Inuishi


Archive | 2002

Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor

Takashi Kono; Katsuyoshi Mitsui; Kiyohiro Furutani


Archive | 1991

Apparatus for forming a thin film on surface of semiconductor substrate

Masanobu Iwasaki; Hiromi Itoh; Akira Tokui; Katsuyoshi Mitsui; Katsuhiro Tsukamoto


Archive | 1992

MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof

Katsuyoshi Mitsui; Shigeki Komori


Archive | 1994

Method of manufacturing a semiconductor device having vertical transistor with tubular double-gate

Katsuyoshi Mitsui

Collaboration


Dive into the Katsuyoshi Mitsui's collaboration.

Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Top Co-Authors

Avatar
Researchain Logo
Decentralizing Knowledge