Kavita Shah

Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation

For the first time we provide a model for describing the LER induced BEOL TDDB lifetime reduction. The model was validated on 50nm ½ pitch copper damascene lines embedded into a k=2.5 low-k material.

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

CMP process optimization for improved compatibility with advanced metal liners

As copper interconnect structures are shrinking with each technology node novel metals other than PVD Ta(N)/Ta are being introduced as barrier materials. These materials act as seed enhancement layers and enable the Cu filling of the narrowest structures. However, the integration of such metals into the manufacturing of sub-35 nm wide Cu lines produces several challenges which need to be addressed. One of these challenges is the compatibility of the interconnect metals with the copper Chemical Mechanical Polishing (CMP) step. In particular, corrosion issues and Cu defectivity in the trenches need to be controlled. An evaluation of the compatibility of the CMP slurries with the new incorporated materials therefore becomes extremely important. Our work shows that by optimizing the CMP process and selecting compatible slurries, novel metals such as CVD Co (combined with a Ta(N) barrier) are promising candidates for the metallization of sub-35 nm lines.

Metallization of sub-30 nm interconnects: Comparison of different liner/seed combinations

Narrow trenches with Critical Dimensions down to 17 nm were patterned in oxide using a sacrificial FIN approach and used to evaluate the scalability of TaN/Ta, RuTa, TaN + Co and MnOx metallization schemes. So far, the RuTa metallization scheme has proved to be the most promising candidate to achieve a successful metallization of 25 nm interconnects, providing high electrical yields and a good compatibility with the slurries used during CMP.