Li-Cheng Shen

Chip Embedded Wafer Level Packaging Technology for Stacked RF-SiP Application

In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric layers, Aginomoto build up film (ABF) in this case. Laser drilling process was adapted to open the via to the pads on the analog chips and digital wafers. The vias and traces were Cu plated to form the interconnection between the chips and the component IO pads. Results of this study show the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. Besides, high aspect ratio build up process by multi-layer ABF lamination and Cu interconnection were well developed. By the described process integration, vertical chip stacked and embedded RF module within 300mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size RF module will be revealed in more detail. Reliability tests such as the 288degC solder dipping and 260degC level 3 preconditioning test were carried out to further clarify the component property. Results of the reliability test and the corresponding failure analysis were described in this paper.

The development of enhanced wafer level packaging

In this paper, one of the wafer level chip scale packaging (WL-CSP) patents issued by ERSO/ITRI, the double elastomer wafer level package, is implemented on the test vehicle of Rambus DRAM to demonstrate the applicability and reliability of WL-CSP for high performance devices. In this design, both thermal and electrical performance enhancements are considered. To demonstrate the reliability of the enhanced WL-CSP, both the component- and board-level criteria are studied, which includes the evaluation of UBM (under bump metallurgy) by adopting low cost electroless and electroplating Ni/Au processes. Results show that the developed thermally and electrically enhanced WL-CSP can pass the reliability tests of pre-con, TC (temperature cycling), PCT (pressure cooker test), and HST (humidity storage test) at component-level and PCT at board-level. Although the board-level TC is on-going, which targets 1000 cycles, early studies of typical FMA are presented here. Moreover, preliminary studies of improving the board-level TC reliability are also included in the paper.

A Novel Design Structure for WLCSP With High Reliability, Low Cost, and Ease of Fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance, and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the coefficient of thermal expansion (CTE) mismatch between silicon and organic printed circuit board (PCB), WLCSP technology is still not fully accepted. We have developed a new solder joint protection-WLCSP (SJP-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged integrated circuits (IC) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.

Characterization of organic multi-mode optical waveguides for the electro-optical printed circuit board (EOPCB)

In this paper, characteristics of optical propagation of the vertical cavity surface emitting laser (850 nm VCSEL) through organic multi-mode optical waveguides are studied. Based on the typical optical loss measurement and the beam profile analysis of optical power distribution, the variation and co-relation between the VCSEL light source and the waveguide outputs are explored. Key factors of waveguide design for EOPCB integration, including the coupling scheme, geometric dimensions, bending, thermal effects, reliability, and etc., are further characterized based on experimental results. A 2.5Gbps optical interconnection prototype using film-type organic array waveguide is also demonstrated here for short reach data-communication at 12 cm.

Wafer level chip stacked module by embedded IC packaging technology

Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV laser drilling process. After surface treatment and seed layer deposition, Cu plating process was adapted for the the via filling and traces patterning to form the interconnection between the chips and the component IO pads. Results of this study showed the benefits of the structure can provide more precise alignment and more reliable chip to wafer stacking without any voids or defects. Meanwhile, the presented wafer level process gives a much simple and cost effective package. By the described process integration, vertical chip stacked and embedded module within 300 mum thickness, excluding the solder ball, could be demonstrated. All the realization of this small size module will be revealed in detail. Severe reliability tests such as the 288degC solder dipping and 260degC level 3 pre-conditioning test were carried out to further clarify the component property. The corresponding failure analysis will be carried out to further clarify the key points of the whole demonstration.

A novel WLCSP technology with high reliability, low cost and ease of fabrication

Wafer level chip scale packaging (WLCSP) has some advantages, such as real die size packaging, high electrical performance and low manufacturing cost. However, because the mechanical reliability of a large die can not be guaranteed due to the CTE (coefficient of thermal expansion) mismatch between silicon and organic PCB (printed circuit board), WLCSP technology is still not fully accepted. We have developed a new SJP-WLCSP (solder joint protection-WLCSP) structure with a delamination layer interposed between the top layer of the chip and the bottom insulating layer of the metal redistribution traces. The stress on the solder joints can be released by the cracks forming in the delamination layer, which protects the solder joints from cracking. Since the cracking of the delamination layer is irrelevant to the electrical circuits of the packaging, the packaged IC (integrated circuits) device remains functional. One of the possibilities for processing the SJP-WLCSP was implemented and validated successfully in the SiLK-wafer samples. The board level packaging samples, using the daisy chain resistance measurement passed 1000 cycles of the temperature cycling testing.

Thermal and Electrical Performance Enhancement with a Cost-Effective Packaging for High Speed Memory Chips

By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type II CiSP, a hybrid process using build-up technologies in wafer level and COG-based (chip-on-glass) transfer bonding is explored to implement the JEDEC-compliant DDR II component. It can be seen that the cost advantages of PCB-like CiSP and the electrical performance of WLP can be achieved simultaneously by adopting this proposed solution. A test vehicle of DDRII-667 memory chips provided by ProMos Technologies Inc. was studied here to demonstrate the feasibility of this developed packaging. Compared with the type I CiSP and the current w-BGA package, the performance is thermally and electrically enhanced.

Reliability and characterization of dielectric layers used for leaded and lead-free solder application

Lots of advanced packaging forms were introduced to meet different application by using the solder balls as the interconnect media between chip and substrate. With the environment protection concerns increasing, lead free solders are playing the more and more important role in this area. The properties and characterization between solder joints and dielectric layers are key reliability issues. The present works mainly focuses on the investigation of the quality of dielectric layers for wafer level chip size packages (WLCSP). In this paper, both the negative tone (Durimide 7510/7320) and positive tone (Durimide 9005) photosensitive materials are evaluated as the dielectric layer for the E-WLCSP. In the E-WLCSP, there were two major bumping processes to be introduced here: Ti/Cu/Ni/Au UBM with 63Sn/Pb eutectic solder and Sn/3.8Ag/0.7Cu lead free solder. The target is to choose the most reliable pairs for positive- and negative-tone polyimides, to meet the different bumping process requirement, and pass the reliability test.