J. De Blauwe

SILC-related effects in flash E/sup 2/PROM's-Part I: A quantitative model for steady-state SILC

In this paper a quantitative model for the steady-state component of the stress induced leakage current (SILC) is developed. The established model is based on the observation of basic degradation monitors on conventional, thermal SiO/sub 2/ gate dielectrics in the thickness range of 6.8-7.1 nm. From a systematic, experimental study, it has been found for the first time that the steady-state SILC, observed after a wide range of constant current stress (CCS) conditions (gate injection polarity), can be uniquely described by a simple, semi-empirical relation, which consists of two parts: 1) the dependence on the measurement field is described as Fowler-Nordheim (FN) tunneling through an oxide barrier of reduced but fixed height (i.e., 0.9 eV), and 2) the level of the SILC at a fixed oxide field is given by the density of neutral bulk oxide traps. Except for a calibration, depending on the oxide thickness and processing, no model parameters have to be adjusted in order to describe all our data. Also, based on bake experiments it has been concluded that interface traps are not causally related to the steady-state SILC in spite of the linear relation which exists between both. Furthermore, these bake experiments provide new evidence that bulk oxide traps play a crucial role in the SILC conduction mechanism.

SILC-related effects in flash E/sup 2/PROM's-Part II: Prediction of steady-state SILC-related disturb characteristics

For Part I see J. de Blauwe et al., vol.45, no.8, pp.1745-50 (1998). In this paper, a new methodology is developed, and applied thereafter, to predict the disturb characteristics of an arbitrary Flash E/sup 2/PROM device which are related to steady-state stress induced leakage current (SILC). This prediction methodology is based on a quantitative model for steady-state SILC, which has been developed on capacitors and nFETs as was reported earlier in Part I. Here, this model is shown to be also valid for tunnel oxide Flash E/sup 2/PROM devices, and used thereafter in a consistent and well-understood cell optimization procedure. The model requires as only input basic cell parameters and an oxide qualification obtained at the capacitor and transistor level.

A new quantitative model to predict SILC-related disturb characteristics in flash E/sup 2/PROM devices

A new quantitative model is developed that allows an excellent prediction of the disturb behavior of tunnel oxide flash E/sup 2/PROM devices after write/erase cycling and provides a well-understood and consistent cell optimization procedure. This model requires as only input a measurement of the oxide quality on capacitors and transistors, and some basic cell characteristics.

A flash memory technology with quasi-virtual ground array for low-cost embedded applications

In this paper, the 0.35-/spl mu/m implementation of a 1-Mb embedded flash memory circuit, based on a split-gate concept, is presented. This concept provides an excellent solution for embedded applications, thanks to the very limited number of processing steps that are needed on top of a baseline CMOS process. Nevertheless, a high performance memory cell is obtained that operates with moderate voltages only. Furthermore, the source-side injection (SSI) mechanism used for cell programming exhibits a very narrow threshold voltage (V/sub t/) distribution, which is maintained even after 1 million program/erase cycles. Because of this tight distribution and the inherent overerase immunity, no additional verification circuitry is needed, which greatly simplifies the decoder design and minimizes the memory footprint. Finally, the memory cell is placed in a quasi-virtual ground array (QVGA) configuration, resulting in a compact memory area with only three quarters of a contact per cell, whereas most arrays require at least a full contact per cell or more.

Read-disturb and endurance of SSI-flash E/sup 2/PROM devices at high operating temperatures

The high-temperature (T) reliability behavior of merged-transistor source side injection (SSI) flash nonvolatile memory (NVM) devices is evaluated in terms of endurance and disturb effects related to stress induced leakage current (SILC) and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room-T, program/erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to an enhanced charge emission. The impact of the operating temperature on SILC-related disturb effects, on the other hand, depends on two combined effects in memory cells where large local charge trap-up influences the threshold voltage, V/sub t/: 1) the T-enhanced trap generation and 2) the T-enhanced emission of trapped charge which influences the disturb field. In the case of the HIMOS-cell-which is discussed here-long-term nonvolatility can still be guaranteed at 150/spl deg/C. Finally, bake tests at higher temperatures (250-300/spl deg/C) have been performed in order to evaluate the persistence of the generated damage. It is found that bulk oxide traps are not cured by the bake and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.

Assessment of oxide reliability and hot carrier degradation in CMOS technology

The techniques and methodologies to be applied in R&D laboratories for the assessment of thin gate dielectrics reliability and hot carrier degradation are reviewed. Examples are given on how the application of these techniques allows to obtain a better insight in the physics of the degradation process. Two such examples are given related to the Dielectric breakdown of thin gate dielectrics and on the Stress-Induced Leakage Current in thin dielectrics.

Impact of tunnel-oxide nitridation on endurance and read-disturb characteristics of Flash E2PROM devices

Abstract Threshold-voltage window closure in non-volatile memory (NVM) devices is known to originate from charge trapping in the dielectric underneath the floating gate (FG dielectric). In this paper, it is shown that oxide nitridation lowers the generation rate of neutral electron traps and, consequently, reduces the amount of trapped charge. Therefore, FG dielectric nitridation improves the endurance characteristics of NVM devices. Also, write/erase ( W E ) degradation of NVM devices results in a Stress Induced Leakage Current (SILC) through the FG dielectric, enhancing read-disturb. The conduction mechanism of the SILC being trap-assisted tunnelling, FG dielectric nitridation is expected to reduce the SILC. However, the lower trap generation rate in the nitrided oxides is compensated by an enhanced trap-assisted conduction efficiency, resulting in nearly the same SILC as compared to conventional oxides. Therefore, read-disturb is barely affected by nitridation of the FG dielectric.

High-temperature reliability behavior of SSI-flash E/sup 2/PROM devices

The high-temperature (T) reliability of merged-transistor Source Side Injection (SSI) Flash NVM devices is evaluated in terms of endurance and SILC-related disturbs, and correlated with the high-T behavior (generation, anneal) of oxide traps. As compared to room T, Program/Erase (P/E) cycling at 150/spl deg/C results in an improved endurance due to enhanced charge emission, but also in a reduction of the read-disturb margin. Also, a bake of 72 hrs. at 250/spl deg/C does not cure the generated damage and, therefore, no long-term relief of SILC-related disturb effects is expected at 150/spl deg/C.