M. Lorenzini

Analytical percolation model for predicting anomalous charge loss in flash memories

Data retention in flash memories is limited by anomalous charge loss. In this work, this phenomenon is modeled with a percolation concept. An analytical model is constructed that relates the charge-loss distribution of moving bits in flash memories with the geometric distribution of oxide traps. The oxide is characterized by a single parameter, the trap density. Combined with a trap-to-trap direct tunneling model, the physical parameters of the electron traps involved in the leakage mechanism are determined. Flash memory failure rate predictions for different oxide qualities, thicknesses and tunnel-oxide voltages are calculated.

Analytical model for failure rate prediction due to anomalous charge loss of flash memories

Anomalous charge loss in flash memories is modeled with a percolation concept. An analytical model is constructed that relates the charge loss distribution of moving bits in flash memories with the geometric distribution of oxide traps, thus linking the phenomenological description of moving bits to physical conduction models. This model allows flash memory failure rate predictions for different oxide qualities and thicknesses.

A new scalable self-aligned dual-bit split-gate charge-trapping memory device

Devices based on charge trapping are a promising solution for Flash memory scaling. The nonconductivity of their storage medium makes them more robust with respect to data loss by charge leakage through the bottom oxide, which, on the contrary sets a hard limit to floating-gate Flash scalability. Their simple processing, highly compatible with CMOS, makes them rapidly integrable into short-term solutions. The well-known SONOS concept however, still suffers from insufficient data throughput and retention. On the other hand, the recently proposed NROM concept, storing two bits in a cell, offers very interesting characteristics by using hot carrier based program/erase operations. However, important drawbacks remain, like insufficient isolation of the bits for scalability, high-power programming, and degradation of the retention after cycling. In this paper, we present a dual-bit trapping device which solves most of these problems by using a split-gate structure which was inspired by the HIMOS concept. The device has a fully self-aligned structure which allows for both bits to be physically isolated in the cell. Those features make it very scalable. Programming can be performed by the very efficient source-side injection mechanism, while erase is done by injection of band-to-band tunneling induced hot holes, which compensate for the trapped electrons. This leads to performances comparable to NROM but with lower power consumption, and lower operating voltages.

Statistical model for stress-induced leakage current and pre-breakdown current jumps in ultra-thin oxide layers

We present a statistical, unified picture of Stress-Induced Leakage Current (SILC) generation, pre-breakdown current steps and breakdown in 2.4 nm oxide layers during a constant voltage stress. Pre-breakdown current steps were investigated through gate voltage ramp measurements and modeled by means of a percolation model with variable trap-trap distance. During oxide stress, first single-trap conduction paths are formed, followed by two-trap conduction paths which are identified as pre-breakdown current steps in small devices. Finally, a highly conducting path is formed which triggers breakdown.

Dynamics of threshold voltage instability in stacked high-k dielectrics: role of the interfacial oxide

In this paper, we focus on comparing the V/sub TH/-instability in scaled stacks with the trapping behavior of thick HfO/sub 2/ layers. We show that a large part of the instability is caused by charging/discharging of HfO/sub 2/ bulk defects, independent of the HfO/sub 2/ thickness. The interfacial oxide thickness influence the mechanism of charging and discharging of the HfO/sub 2/ defects.

Comparative reliability investigation of different nitride based local charge trapping memory devices

The paper compares the endurance and retention characteristics of two charge trapping devices having different electron injection points and the same hole injection points. We found that hole trapping in the bottom oxide can explain the different endurance behavior of both devices, and the degradation of their retention after cycling.

Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies

The electro-static discharge (ESD) breakdown mechanism of 90 nm MOSFET n+/pwell devices is described in detail and modelled with a physics based equation set. The newly developed consistent parameter extraction approach allows to overcome the limitations of existing methodologies, which are not applicable for the 90 nm CMOS node device behaviour, and to calibrate precisely the snapback models. These models will help optimising the ESD robust I/O cells, which use 90 nm MOSFET devices as I/O drivers and ESD structures.

Modelling of the hole-initiated impact ionization current in the framework of hydrodynamic equations

Abstract Several research papers have shown the feasibility of the hydrodynamic transport model to investigate impact ionization in semiconductor devices by means of mean-energy-dependent generation rates. However, the analysis has been usually carried out for the case of the electron-initiated impact ionization process and less attention has been paid to the modelling of the generation rate due to impact ionization events initiated by holes. This paper therefore presents an original model for the hole-initiated impact ionization in silicon and validates it by comparing simulation results with substrate currents taken from p-channel transistors manufactured in a 0.35 μm CMOS technology having three different channel lengths. The experimental data are successfully reproduced over a wide range of applied voltages using only one fitting parameter. Since the impact ionization of holes triggers the mechanism responsible for the back-bias enhanced gate current in deep submicron nMOS devices, the model can be exploited in the development of non-volatile memories programmed by secondary electron injection.

Study of Secondary Electron Injection Phenomena in Deep Sub-micron MOSFETs and Flash Cells

* Also with EE department, K.U.Leuven Abstract We investigated the secondary electron injection phenomena in deep sub-micron MOSFETs and Flash cells. Charge pumping analysis shows a different lateral interface trap profile caused by secondary electron injection from that induced by conventional hot electron injection. This proves a shift of injection point of secondary electrons toward the source side. A large gate injection current has been found in a split gate Flash cell, which leads to a novel Flash memory cell concept suitable for low voltage, high density embedded applications.

Time Dependent Anomalous Charge Loss Modeling in Flash Memories and an Accelerated Testing Procedure

Data retention is the most critical issue of nonvolatile memories (NVM). Because of the decreasing tunnel oxide thickness, this data retention is determined by a limited population of bits with larger than expected charge loss. This anomalous charge loss has generally been ascribed to the high-field stress during the (tunnel) erase operation. Although several models have been suggested Il-5], up till now there is no commonly accepted charge loss model available. In this paper the direct tunneling model (DT) is proposed to describe the transient behavior of anomalous charge loss, to model accelerated testing by drain disturb, and to derive a simplified analytical method for failure rate prediction.