M. Rack

Noise coupling between TSVs and active devices: Planar nMOSFETs vs. nFinFETs

Through Silicon vias (TSVs) are a key breakthrough in 3D technology to shorten global interconnects and enable the heterogeneous integration. However, TSVs also introduce an important source of noise coupling arising from electrical coupling between TSVs and the active devices. This paper investigates the TSV noise coupling to active devices including both FinFETs and planar transistors based on two-port S-parameter measurements up to 40 GHz. The measurements clearly show that nFinFETs have better noise coupling immunity than planar nNMOSFETs. The dominant coupling mechanisms were also identified for both types of active devices. Moreover, calibrated TCAD models were developed. We show that via-last TSV architectures with thick liners (“donut TSVs”) and scaled TSV diameters reduce the noise coupling to active devices. Finally, both coupling and stress induced saturation current variations as a function of TSV to active devices distance were investigated. This allows us to propose a novel model for the TSV Keep Out Zone (KOZ) including electromagnetic coupling effects.

Modeling the effect of charges in the back side passivation layer on through silicon via (TSV) capacitance after wafer thinning

Evaluating the importance of electromagnetic (EM) coupling from through silicon vias (TSVs) has become crucial to the design of three-dimensional integrated circuits (3D-ICs). One of the most important parasitic contributions to signal propagation in 3D-ICs is the TSV capacitance. It is both frequency and bias dependent since a TSV is a metal-oxide-semiconductor (MOS) structure. In this work, anomalous TSV capacitance behavior after wafer thinning is reported and investigated by combining measurements and finite element (FEM) semiconductor simulations. Excellent agreement between models and experimental data confirms the origin of the anomalous TSV capacitance behavior: the presence of fixed charges in the back side (BS) passivation layer of the TSV after wafer thinning. In addition, a BS inversion layer can act as a conductive channel between neighboring vias, increasing the capacitive coupling between TSVs. Calibrated equivalent circuit models of the TSV in contact with a BS inversion layer are proposed for the first time in the context of 3D integration and validated.

Fast and Accurate Modelling of Large TSV Arrays in 3D-ICs Using a 3D Circuit Model Validated Against Full-Wave FEM Simulations and RF Measurements

This paper presents a 3D circuit model capable of rapidly and accurately evaluating substrate noise coupling in the context of 3D integration. Since TSVs are large and noisy structures, the evaluation of electromagnetic coupling to and from TSVs has become crucial to the design of three-dimensional integrated circuits. In this work, we present a fast and accurate 3D circuit model to this end. The model is verified against full-wave simulations and wideband Sparameter measurements of three different TSV structures, including guard rings and up to four TSVs. The model maintains the accuracy of full-wave simulations while presenting a speed increase of 2 to 3 orders of magnitude. This features enables the model to investigate the coupling parameters and crosstalk voltages in very large and complex 3D volumes. Our powerful model provides new opportunities in large scale analysis, and as an example an 11x11 TSV array is simulated in both frequency-and time-domain over a wide frequency band including 121 TSVs and circuit nodes.

Through silicon via to FinFET noise coupling in 3-D integrated circuits

High speed TSV signals can penetrate through the dielectric liner material, transfer in the silicon substrate and degrade the performance of FEOL devices. In this paper we investigate TSV noise coupling to active device including both FinFET and planar transistors. Calibrated TCAD models are used to perform time domain analysis and understand the mechanisms of substrate noise interaction with active device. Parametric simulations are performed in order to understand the tradeoffs among different design parameters. The results demonstrate superior substrate noise immunity of FinFETs over equivalent planar transistors. In addition we show that a scaled TSV diameter, a novel TSV architecture with thick polymer liner, placing the substrate contact closer to active device and a TSV guard ring helps to mitigate the TSV noise. Finally the importance of electromagnetic coupling effects on Keep Out Zone (KOZ) extraction is illustrated.

RF harmonic distortion modeling in silicon-based substrates including non-equilibrium carrier dynamics

In this paper, a simulation methodology is presented that takes carrier dynamics into account, disallowing instantaneous changes in substrate carrier concentrations, and providing more accurate estimations of harmonic distortion (HD) components. Using this method, we simulated the HD components introduced in a CPW line on various flavors of Si-based substrates. The results are compared to measured HD components over a wide range of bias points and at three fundamental excitation frequencies from 900 MHz to 4 GHz. It is shown that carrier relaxation times are of first importance for understanding the HD levels introduced by Si-substrates at RF frequencies and above. Further-more, characteristic dips in the extracted HD components, for increasing fundamental power, are evaluated and shown to be tightly linked to the position of the devices DC bias voltage relative to the substrates flatband voltage. The new simulation tool is also capable of capturing these typical dips in the HD curves, and provides physical insight into the reasons behind their existence.

Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning

This paper investigates the influence of TSV noise coupling on nearby devices based on an extended 3D TSV circuit model. This model not only takes into account the complex RF field distributions in bulk Si, but also incorporates the anomalous TSV capacitance inversion behavior, which has been found to occur due to the presence of fixed charges in the backside passivation layer after wafer thinning. The extended 3D TSV circuit model is validated by the excellent agreement between the simulation results and experimental data. It demonstrates that the inversion behavior of the TSV capacitance increases the noise coupling to adjacent devices mainly in the low frequency range. Furthermore, we show that noise mitigation techniques can be easily implemented in this 3D circuit model to predict the extent of noise coupling alleviation.