Masanori Odaka

Advanced BiCMOS technology for high speed VLSI

This paper describes the high performance BiCMOS (Hi-BiCMOS) device technology and discusses the scalability to sub-micron. As the device structure is scaled down from 2 µm to 1.3 µm, BiCMOS circuit performance is improved by the factor of the scaling. By further scale down to 0.8 µm, a 0.27 ns gate delay in BiCMOS gate and 5.5 ns access time of 64kbit BiCNOS ECL RAN are expected.

High speed BiCMOS VLSI technology with buried twin well structure

Bipolar transistors of high cut off frequency (f_{T}=9GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.

A 13ns/500mW 64Kb ECL RAM

This paper will cover the design of a 16K×4 SRAM which uses buried twin-well 2μm CMOS transistors and 4GHz cutoff frequency bipolar transistors. The circuit combines a high-resistance polysilicon - load NMOS memory cell with mixed MOS/bipolar periphery circuits to achieve ECL compatibility, 13ns access times and an operating power of 500mW at 40MHz.

A 512 kb/5 ns BiCMOS RAM with 1 kG/150 ps logic gate array

An ECL (emitter-coupled-logic) 512-kb BiCMOS SRAM (statistic random access memory) with 1-kG logic and using 0.8- mu m high-performance bipolar CMOS (Hi-BiCMOS) technology is described. The RAM has 5-ns address access time and 2-ns write-pulse width. The logic gate has 150-ps propagation delay with 4-mW power dissipation. A RAM-with-logic configuration is adopted to eliminate interconnection delay between the RAM and peripheral logic and to facilitate a wide-bit RAM. The design rule dependence of the delay time of a three-input ECL OR/NOR gate and a two-input BiCMOS NAND gate is shown. On-chip address access times, under 5 ns from address latches to data-out latches at room temperature with a marching test pattern, are also shown. Major characteristics of the LSI are presented.<<ETX>>

A 7ns/350mW 64K ECL compatible RAM

A 64K×1 ECL RAM using 1.3μm bipolar-CMOS technology including bipolar transistor with a 7GHz cutoff frequency will be presented. Variable impedance and equalizing circuitry permit 7ns access time. Power dissipation is 350mW.

A 16ns 16K bipolar RAM

A 16ns 150mW ECL compatible static RAM will be described. Cell and die size of 569μm²and 16.4mm²have been achieved with oxide-isolated poly silicon-walled emitter transistors.

A powerful yet ecological parallel processing system using execution-based adaptive power-down control and compact quadruple-precision assist FPUs

This paper reports the first trial in which spatially and temporally fine-grained power-down control has been implemented in a high-performance processor in the sense that the FPUs are controlled spatially and dynamically based on the execution sequence.

Logic-in-memory VLSI for mainframe computers

A bipolar 6Kb memory VLSI with 770 logic gates developed for virtual address translation and buffer storage control will be described. Access time and power dissipation are 6.7ns and 5.2W.

Technology improvement for high speed ECL RAMs

The trends in high speed ECL random access memories (RAMs) are reviewed with emphasis on memory cell improvements for achieving high speed performance. State-of-the-art technologies including bipolar, BICMOS, memory-with-logic modules and logic-in-memory LSIs are discussed. Finally, some prospects for ultra-high speed RAMs are proposed.