H. Miyoshi

16 Mb DRAM/SOI technologies for sub-1 V operation

Extra low voltage DRAM/SOI technologies were developed using (1) modified MESA isolation without parasitic MOS operation, (2) dual gate CMOS for low Vth control, (3) optimized layout using both body-tied and floating body MOSFETs, and (4) reduced Cb/Cs ratio. Completely redesigned low voltage scheme 16 MDRAM/SOI was successfully realized and functional operation was obtained at very low supply voltage below 1 V.

Approaches to extra low voltage DRAM operation by SOI-DRAM

The newly designed scheme for a low-voltage 16 MDRAM/SOI has been successfully realized and the functional DRAM operation has been obtained at very low supply voltage below 1 V. The key process and circuit technologies for low-voltage/high-speed SOI-DRAM will be described here. The extra low voltage DRAM technologies are composed of the modified MESA isolation without parasitic MOS operation, the dual gate SOI-MOSFETs with tied or floating bodies optimized for DRAM specific circuits, the conventional stacked capacitor with increased capacitance by thinner dielectric film, and the other bulk-Si compatible DRAM structure. Moreover, a body bias control technique was applied for body-tied MOSFETs to realize high performance even at low voltage. Integrating the above technologies in the newly designed 0.5-/spl mu/m 16 MDRAM, high-speed DRAM operation of less than 50 ns has been obtained at low supply voltage of 1 V.

An asymmetric memory cell using a C-TFT for ULSI SRAMs

A compact SRAM memory cell structure using a set of C-TFTs (complementary thin-film transistors) is discussed. A C-TFT is composed of a top-gate N-channel TFT and a bottom-gate P-channel TFT. The proposed cells size was reduced to 80% of that of a conventional one at the 16-Mb SRAM level. Also, a stable read operation under a low-supply voltage could be realized by using a C-TFT.<<ETX>>

The applications of the high-pressure oxidation process to the fabrication of MOS LSI

The applications of the high-pressure oxidation method to the fabrication of MOS LSI are described. High-pressure selective oxidation of silicon with the use of silicon nitride film as a mask was investigated. Oxidation-induced stacking faults were found to be reduced significantly by the high-pressure steam oxidation compared with the conventional wet O2atmospheric oxidation. The refresh time characteristics in a 16 384-bit MOS dynamic RAM were improved by using the high-pressure oxidation method. Furthermore, a simpler process to grow simultaneously thin- and thick-oxide layers used for the transistors in the MOS RAM with double polysilicon structure was provided.

Microscopic and statistical approach to SILC characteristics-exponential relation between distributed Fowler Nordheim coefficients and its physical interpretation

Microscopic characteristics of stress-induced leakage current (mSILC) are studied by analyzing a large amount of data on the charge retention characteristic of stacked gate arrayed transistors. It is found that the SILC characteristics fluctuate in the microscopic regions, but they all fit the Fowler Nordheim (F-N) formula. Moreover, the coefficients /spl alpha/ and /spl beta/ of the F-N equation, which are conventionally constants, are obtained in this study by statistically analyzing mSILC characteristics, and are therefore distributed, with a strong exponential relation to each other. It is found that this correlation can be qualitatively explained by the analytical trap-trap transition model.

Identification of stress-induced leakage current components and the corresponding trap models in SiO/sub 2/ films [MOS transistors]

Time-decay stress-induced leakage current (SILC) has been systematically investigated for the cases of both Fowler-Nordheim (FN) stress and substrate hot-hole stress. From the three viewpoints of the reproducibility of the current component for the gate voltage scan, the change of oxide charge during the gate voltage scan, and the resistance of the current component to thermal annealing, it has been found that time-decay stress-induced leakage current is composed of five current components, regardless of stress type. Trap models corresponding to each current component have been proposed. In addition, it has also been proven that holes generate the electron traps related to one of those current components.

Low voltage operation of sub-quarter micron W-polycide dual gate CMOS with non-uniformly doped channel

A 0.25 /spl mu/m W-polycide dual gate CMOS has been newly developed for a logic in DRAM under low voltage operation. A novel gate electrode can eliminate inter-diffusion and the gate depletion using a barrier oxide film against dopant diffusion, so that a dual gate CMOS can be fabricated with sufficient thermal budget. Moreover, low threshold voltage and high current drivability can be obtained by a non-uniformly doped channel structure formed by the oblique rotational ion implantation utilizing W-polycide gate as a mask. As a result, a high performance has been achieved.

Substrate Engineering for Reduction of Alpha-Particle-Induced Charge Collection Efficiency

Measurements of alpha-particle-induced charge collection efficiency (CCE) together with simulation analysis have been carried out for several types of substrates: a double well, a p-well in a p- epitaxial layer grown on p+ substrate (epi-substrate) and a p-well with a buried defect layer. As a result, the following have been clarified. CCE for the double well is low because the bottom n-layer acts as an effective electron absorber. CCE for the p-well in the epi-substrate increases with increase in the thickness of the epilayer because the potential difference between the heavily doped substrate and the lightly doped epilayer forms a barrier which prevents electrons from traveling into the substrate. Even for the p-well in a thin epilayer, CCE is comparable to that for the p-well in the conventional p- substrate. CCE for the p-well with a buried defect layer formed by high-energy and high-dosage ion implantation is as low as CCE for the double well because the carrier lifetime is short in the buried layer due to lattice defects.

The effects on metal oxide semiconductor field effect transistor properties of nitrogen implantation into p+ polysilicon gate

We have studied in detail the effects of nitrogen implantation into a p+ polysilicon gate on gate oxide properties for the surface p-channel metal oxide semiconductor (PMOS) below 0.25 µm. The nitrided oxide film can be easily formed by the pile-up of nitrogen into the gate oxide film from the polysilicon gate. It was found that boron penetration through the gate oxide film can be effectively suppressed by nitrogen implantation into a p+ polysilicon gate because nitrogen in the polysilicon film can suppress boron diffusion, and the nitrided oxide film can also act as a barrier to boron diffusion. Moreover the hot-carrier hardness can be remarkably improved by the nitrided oxide film since interface state generation can be suppressed by the nitrided oxide film. Furthermore the number of electron traps in the gate oxide film can also be reduced by nitrogen implantation.

Clarification of nitridation effect on oxide formation methods

The electrical characteristics of gate dielectrics have been intensively studied. We examined four types of gate dielectrics: thermal oxide films formed in a pyrogenic steam ambient, those in a dry oxygen ambient, chemical vapor deposition (CVD) oxide films, and the thermal/CVD stacked oxide films. The effects of nitridation on oxide properties have been also systematically investigated using the nitrogen implantation technique. It is found that hot-carrier degradation can be improved by nitridation irrespective of the oxidation methods. This improvement is attributed to the suppression of interface state generation and the reduction in the number of electron traps in the oxide films. Our extensive investigation concludes that the nitridation of gate oxide films by nitrogen implantation is very promising for the improvement in reliability in spite of the difference in oxide formation methods.