Naim Moumen

Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility

HfO2 films have been grown with two atomic layer deposition (ALD) chemistries: (a) tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and (b) HfCl4+H2O. The resulting films were studied as a function of ALD cycle number on Si(100) surfaces prepared with chemical oxide, HF last, and NH3 annealing. TEMAHf+O3 growth is independent of surface preparation, while HfCl4+H2O shows a surface dependence. Rutherford backscattering shows that HfCl4+H2O coverage per cycle is l3% of a monolayer on chemical oxide while TEMAHf+O3 coverage per cycle is 23% of a monolayer independent of surface. Low energy ion scattering, x-ray reflectivity, and x-ray photoelectron spectroscopy were used to understand film continuity, density, and chemical bonding. TEMAHf+O3 ALD shows continuous films, density >9g∕cm3, and bulk Hf–O bonding after 15 cycles [physical thickness (Tphys)=1.2±0.2nm] even on H-terminated Si(100). Conversely, on H-terminated Si(100), HfCl4+H2O requires 50 cycles (Tphys∼3nm) for continuous films and bulk Hf–O bonding. ...

In situ infrared spectroscopy of hafnium oxide growth on hydrogen-terminated silicon surfaces by atomic layer deposition

The interface formation between HfO2 and H-terminated Si(111) and Si(100) is studied by in situ infrared absorption spectroscopy during atomic layer deposition using alternating tetrakis-ethylmethylamino hafnium (TEMAH) and deuterium oxide (D2O) pulses. The HfO2 growth is initiated by the reaction of TEMAH with Si–H rather than D2O, and there is no evidence for SiO2 formation at moderate growth temperatures (∼100°C). Although Rutherford backscattering shows a linear increase of Hf coverage, direct observations of Si–H, Si–O–Hf, and HfO2 phonons indicate that five cycles are needed to reach the steady state interface composition of ∼50% reacted sites. The formation of interfacial SiO2 (∼0.7nm) is observed after postdeposition annealing at 700°C in ultrapure nitrogen.

Interfacial Layer-Induced Mobility Degradation in High-

Analysis of electrical and scanning transmission electron microscopy (STEM) and electron energy loss spectra (EELS) data suggests that Hf-based high-k dielectrics deposited on a SiO2 layer modifies the oxygen content of the latter resulting in reduction of the oxide energy band gap and correspondingly increasing its k value. High-k deposition on thinner SiO2 films, below 1.1 nm, may lead to the formation of a highly oxygen deficient amorphous interfacial layer adjacent to the Si substrate. This layer was identified as an important factor contributing to mobility degradation in high-k transistors.

k

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Transistors

The development of wet-etch chemistries using standard fab chemicals and tools has been studied to successfully integrate dual work function metal gate CMOS. Candidate gate materials studied were TiN, Ta, TaN and TaSiN. Two hard mask materials, amorphous silicon (am-Si) and TEOS, and two gate dielectric films, Atomic Layer Deposition (ALD) HfO 2 and HfSi x O y , were also studied for their etch selectivity to various chemical formulations. In addition, some preliminary electrical results of devices processed using this wet-etch module have been reported here.

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, (i) reduction of the bottom interfacial layer (BIL) using NH 3 interface engineering, (ii) thickness reduction of the HfO 2 dielectric, and (iii) use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the NH 3 BIL with scaled HfO 2 /metal gates and 0.81 nm EOT using the O 3 BIL with scaled HfO 2 /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed.

Metal Wet Etch Process Development for Dual Metal Gate CMOS

We report that precursor HfCl4 plays an important role in optimizing atomic-layer-deposition HfO2 bulk trapping characteristics. By systematic study, it has been observed that, under certain optimized precursor pulse time condition (450ms pulse as compared to standard 150ms), bulk trapping characteristics could be improved significantly without affecting the equivalent oxide thickness and leakage current characteristics of the devices. Slight improvement in mobility of the devices could also be obtained. Secondary-ion-mass-spectroscopy analysis shows that increase in the chlorine composition by increasing precursor pulse time could be attributed to the observed improvement. Drastic increase in pulse time (1500ms) negates the benefit.

Subnanometer Scaling of HfO2/Metal Electrode Gate Stacks

Growth at moderate temperatures, below ∼100°C, is shown to prevent interfacial silicon oxidation during atomic layer deposition of high-permittivity (high-K) gate dielectrics on hydrogen-terminated Si(100). Trimethylaluminum, employed for aluminum oxide growth, leaves the hydrogen layer completely intact. Tetrakis(ethylmethylamido)hafnium partially scavenges the hydrogen layer during hafnium oxide nucleation, resulting in an interface composed of H-terminated silicon atoms and Si-O-Hf bridges. In both cases, high-K dielectrics are grown without formation of interfacial SiO 2 . Once grown at low temperatures, subnanometer Al 2 O 3 layers effectively prevent interfacial SiO 2 formation during subsequent growth at higher temperatures required for optimum high-K quality. This two-step deposition scheme may thereby be useful for gate-stack scaling.

Optimization of precursor pulse time in improving bulk trapping characteristics of atomic-layer-deposition HfO2 gate oxides

Thermal nitridation of H∕Si(100) surfaces with NH3 gas has been studied as a pretreatment for atomic layer deposition of Al2O3. The chemical nature of both the nitride interface and the Al2O3 growth was characterized using in situ transmission infrared spectroscopy and medium energy ion scattering. Nitride layers thicker than 3–4A provide an effective barrier against interfacial SiO2 formation and promote the nucleation of Al2O3 growth.

Hydrogen Barrier Layer Against Silicon Oxidation during Atomic Layer Deposition of Al2O3 and HfO2

Electrical properties of a wide range of Hf-based gate stacks were investigated using several modifications of a standard planar CMOS process flow to address the effects of transistor processing on the electrical properties of the high-k dielectrics. Characteristics of the short channel transistors were shown to be very sensitive to the fabrication process specifics - process sequence, tools, and recipes. It was concluded that, contrary to SiO/sub 2/, the high-k films could be contaminated with reactive species during the post-gate definition fabrication steps, resulting in the formation of local charge centers. Such process-induced charging (PIC) degrades transistor performance and complicates evaluation of the intrinsic properties of high-k dielectrics. A process scheme that minimizes PIC is discussed.