Oliver Ansell

Plasma etch and low temperature PECVD processes for via reveal applications

This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >;5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ~200:1 can be achieved on bonded TSV wafers. A novel end-point detection method will also be presented allowing control of the reveal height. The ability to tune the uniformity from centre fast to edge fast will also be covered. A range of stable, repeatable, dielectric films will be presented having a deposition temperature <;180°C and no moisture uptake. These films will also be shown to have highly conformal via tip coverage and excellent electrical properties, with breakdown voltages >;10 MV/cm and leakage current densities <;1E-9 A/cm2 at 2MV/cm.

Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking

Wafer-to-wafer 3D integration has a potential to minimize the Si thickness, which enables us to connect multiple wafers with significantly scaled through-Si vias. In order to achieve this type of 3D structure, backside thinning is a key step. Conventional mechanical grinding is known as the best way to remove bulk Si in terms of cost of ownership (CoO). However, mechanical damage such as induced dislocations needs to be removed after extreme thinning to avoid a serious impact on the device performance. CMP shows the best performance in terms of roughness with a significantly flat surface with only atomic step roughness. Furthermore, the existing mono-vacancies are as low as for a bulk Si substrate. However the total thickness variation (TTV) worsens as more Si is removed. The dry etch process enables a faster etch rate than CMP and wet etching. Furthermore, the mono-vacancy/damage layer after dry etching is equivalent to that achieved when combined with CMP. The combination of CMP and dry etch enables us to achieve extreme thinning of active device wafers (<;5 μm) with minimal roughness, no damage layer (mono-vacancy) and no edge delamination.

A new plasma source for next generation MEMS deep Si etching: Minimal tilt, improved profile uniformity and higher etch rates

The demand for evermore sensitive MEMS sensor devices, such as gyroscopes, has driven the need for the manufacturing processes to deliver smaller tolerances. This is especially evident when considering the DRIE process used to fabricate the intricate sensor features on the silicon wafer. Aspect ratios have become higher with CDs reducing and etch depths increasing. But of particular significance when referring to MEMS gyroscopes is profile tilt. Device design and signal processing can no longer compensate for innate tilt, and so the manufacturing methods have to improve to deliver the levels of tilt necessary for the next generation of devices at a cost effective throughput. This paper will describe data from a new plasma source design, the Pegasus Rapier, employed to improve the tilt performance of the Bosch DRIE process [1] for the productionisation of next generation MEMS gyroscopes. This data will show <±0.15° profile tilt capability on 200mm wafers at rates of 7µm/min for a 20:1 aspect ratio trench.

Extreme wafer thinning optimization for via-last applications

As the 3D interconnect density is increasing exponentially when scaling to lower levels of the interconnect wiring, we see that very soon 3D interconnect pitches of 5 μm and below will be required. Current 3D-SIC (3D-Stacked IC) technologies do not yet offer such interconnect densities and it is expected that most of the 3D-SOC (3D System On Chip) integration technology schemes will require a wafer-to-wafer (W2W) bonding approach. The wafer thinning process becomes very critical when final Si thicknesses of the top wafer in the 5μm range or below are considered. Indeed, a good control of the final Si thickness as well as the total thickness variation (TTV) are necessary to enable a stable via-last etch process with minimum undercut (notching). Two extreme wafer thinning approaches are investigated and compared in terms of process performance and cost of ownership.

Considerations and benefits of plasma etch based wafer dicing

Wafer dicing has been traditionally carried out using mechanical methods, including diamond saw and laser techniques. However, these techniques are imperfect, in that there is a need to manage the damage caused by them through compromises in pattern density and throughput. However, for power devices, chip cards and LEDs, the trends are towards thinner wafers and smaller die sizes, and these compromises further undermine the conventional dicing methods and render them less cost effective. For other devices, including bio-compatible MEMS, conventional dicing is unable to provide the level of cleanliness required. This paper will describe how the use of silicon plasma etching can produce a step change in dicing capability, even for the thin wafer scenario described above, that will provide increased die densities, increased throughputs and improved device reliability.

Singulation by Plasma Etching: Integration Techniques to Enable Low Damage, High Productivity Dicing

Plasma dicing has rapidly gained traction as a viable alternative to conventional blade and laser techniques for wafer singulation. This has been due mostly to the significant benefits plasma dicing delivers in relation to the quality and reliability of devices singulated in this manner.Key to the successful integration of plasma dicing, into the established hierarchy of singulation techniques, is how the ancillary parts of the process flow can be utilized or adapted to accommodate it. More importantly, is the ease at which this can happen and also, how implementation can be achieved in a cost effective manner.Copyright

Claritas TM — A unique and robust endpoint technology for silicon drie processes with open area down to 0.05%

Endpoint detection (EPD) is a critical control functionality for many etch processes, especially for deep silicon etches [1] that terminate on an underlayer. Where this device structure is employed, it is vital that the point at which the etch process reaches the underlayer is detected as promptly as possible. This allows for proper management of the overetch to clear all features to the underlayer without running for longer than necessary and introducing lateral notching to the base of the feature [2]. As device requirements have become more stringent, lower open areas and higher aspect ratios have necessitated development of more sensitive techniques to achieve successful endpoint detection and overetch control.