Oxana Chamirian

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co-Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co-Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni2Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of ∼ 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi2 at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.

Silicides for the 100-nm node and beyond: Co-silicide, Co(Ni)-silicide and Ni-silicide

As scaling progresses, conventional Co/Ti silicidation is facing difficulties related to the nucleation of the low resistive Co-disilicide phase during the second RTP step of silicidation. When linewidths, junction depths and silicide thicknesses are being reduced, the RTP2 thermal process window narrows down rapidly. It is expected that the process window can be widened by alloying the Co film with Ni, because the presence of Ni lowers the nucleation barrier for the Co-disilicide phase. Replacing Co-disilicide by Ni-monosilicide is a promising alternative because the same silicide sheet resistance can be obtained with 35% less silicon consumption.

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi2 were possible for thicker films depending on anneal temperature and time. Activation energy of ∼2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi2 is higher than for morphological degradation.

Applications of Ni-based silicides to 45 nm CMOS and Beyond

This paper presents an overview of Ni-alloy (Ni, Ni-Pt and Ni-Ta) silicide development for the 45 nm node and beyond, including applications to self-aligned silicide (SALICIDE) processes, reaction with SiGe and strained Si on SiGe, and applications to fully silicided (FUSI) gates. Key SALICIDE issues addressed include the use of spike or low temperature rapid thermal processes (RTP) to control silicidation and junction leakage on small features, factors affecting the formation of epitaxial pyramidal NiSi 2 grains, and NiSi thermal stability and agglomeration kinetics. Alloying with Pt or Ta is shown to improve thermal stability of NiSi films, although with quite different behaviors. While Pt is incorporated predominantly in solution in NiSi, Ta segregates to the surface of the films. Ni-Pt alloy silicides were also found to achieve low sheet resistance on narrow gates, low contact resistivity and low junction leakage, making them attractive for CMOS applications. For the Ni/SiGe reaction, a narrower RTP process window for low sheet resistance and a lower activation energy for agglomeration were observed when compared to the Ni/Si reaction. The lower thermal stability was correlated to Ge segregation from the Ni(SiGe) films. The Ni/doped poly-Si reaction was studied for FUSI gate applications, showing a retardation of the silicidation kinetics for high B doses and a large pile- up of dopants (for As, B or P) at the NiSi/SiO 2 interface due to dopant snowplow during silicidation. The work function (WF) of NiSi was observed to shift with the addition of dopants, effect attributed to modifications of the interface dipole by the pile-up of dopants. No significant degradation was observed when comparing gate oxide breakdown statistics for Ni FUSI to conventional poly-Si gates. The process window for a FUSI gate-last process (performed after S/D Ni silicidation) was evaluated showing a potential integration problem due to possible degradation of the S/D silicide during the FUSI gate reaction.

Study of CoSi 2 formation from a Co-Ni alloy

CoSi2 formation from Co-Ni alloys with 25 and 10% Ni content was investigated. Samples with various Co-Ni/Ti stacks were characterized by four-point probe, AES, XRD, RBS and TEM. Light scattering measurements were carried out for roughness evaluation. Stress build-up was estimated from room temperature measurements of wafer curvature. It was found that Co disilicide formation temperature decreases with an increase of the Ni percentage. CoSi2 growth at temperatures around 450-500°C depending on Ni concentration and Ti cap thickness was observed. Sheet resistance of 5-6.5 Ω/sq. was measured for various Co-Ni/Ti compositions. CoSi2(220) and CoSi2(111) peaks were detected on XRD spectra for both Ni-rich and Ni-poor layer. Stress values of 0.9-1.9 GPa were calculated for silicidation of various Co-Ni/Ti stacks. The roughness of the silicide film was found to be dependent on Ni concentration, Ti cap thickness and anneal temperature.

CoSi 2 formation from Co x Ni 1-x /Ti system

The presence of Ni can significantly promote the CoSi-CoSi2 transformation process reducing the transformation temperature and, in consequence, the thermal budget of silicidation. In this work, silicidation of the Si/Co0.95Ni0.05/Ti system was investigated. Four point probe (4PP), Auger electron spectroscopy (AES), X-ray diffraction (XRD), Rutherford backscattering spectroscopy (RBS), and transmission electron microscopy (TEM) were used to characterise the silicide films. It was found that Co-Ni silicide can be formed at lower temperatures compared to the pure Co/Ti process, at the same time keeping important properties such as sheet resistance and roughness close to those of pure CoSi2.

Linewidth Dependence of the Reverse Bias Junction Leakage for Co-Silicided Source/Drain Junctions

In this work the reverse bias junction leakage was studied for Co-silicided 100 nm deep As source/drain junctions. The effect of pre-clean and silicidation temperature was investigated. The area component of the leakage current was found to be dominant for silicided source/drain areas wider than 1 mm. Increasing the thermal budget for silicidation was found to improve the area leakage. For diodes consisting of active area stripes narrower than 0.5 μm, the leakage current is no longer improved by increasing the silicidation temperature. As a result the leakage current is found to depend strongly on the active area linewidth. It was found that the linewidth dependence of the junction leakage cannot be attributed to silicide induced stress. It is argued that the higher leakage current observed for narrow lines can be attributed to the stress induced by the STI isolation and to increased silicide thickness in the narrow active lines