P. Kozlowski

Ultrathin high-K gate stacks for advanced CMOS devices

Reviews recent progress in and outlines the issues for high-K high-temperature (/spl sim/1000/spl deg/C) poly-Si CMOS processes and devices and also demonstrate possible solutions. Specifically, we discuss device characteristics such as gate leakage currents, flatband voltage shifts, charge trapping, channel mobility, as well as integration and processing aspects. Results on a variety of high-K candidates including HfO/sub 2/, Al/sub 2/O/sub 3/, HfO/sub 2//Al/sub 2/O/sub 3/, ZrO/sub 2/, silicates, and AlN/sub y/(O/sub x/) deposited on silicon by different deposition techniques are shown to illustrate the complex issues for high-K dielectric integration into current Si technology.

Electrical characterization of germanium p-channel MOSFETs

In this letter, we report germanium (Ge) p-channel MOSFETs with a thin gate stack of Ge oxynitride and low-temperature oxide (LTO) on bulk Ge substrate without a silicon (Si) cap layer. The fabricated devices show 2 /spl times/ higher transconductance and /spl sim/ 40% hole mobility enhancement over the Si control with a thermal SiO/sub 2/ gate dielectric, as well as the excellent subthreshold characteristics. For the first time, we demonstrate Ge MOSFETs with less than 100-mV/dec subthreshold slope.

Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications

We present a new ETSOI CMOS integration scheme. The new process flow incorporates all benefits from our previous unipolar work. Only a single mask level is required to form raised source/drain (RSD) and extensions for both NFET and PFET. Another new feature of this work is the incorporation of two strain techniques to boost performance, (1) Si:C RSD for NFET and SiGe RSD for PFET, and (2) enhanced stress liner effect coupling with faceted RSD. Using the new flow and the stress boosters we demonstrate NFET and PFET drive currents of 640 and 490 µA/µm, respectively, at Ioff = 300 pA/µm, VDD = 0.9V, and LG = 25nm. Respectable device performance along with low GIDL makes these devices attractive for low power applications. Record low VT variability is achieved with AVt of 1.25 mV·µm in our high-k/metal-gate ETSOI. The new process flow is also capable of supporting devices with multiple gate dielectric thicknesses as well as analog devices which are demonstrated with excellent transconductance and matching characteristics.

High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric

We report Ge p-channel MOSFETs with a thin gate stack of Ge oxynitride and LTO on bulk Ge substrate without a Si cap layer. Excellent device characteristics (IV and CV) are achieved with subthreshold slope 82mV/dec. /spl sim/40% hole mobility enhancement is obtained over the Si control with a thermal SiO/sub 2/ gate dielectric. To our knowledge, this is the first demonstration of Ge MOSFETs with less than 10nm thick gate dielectric and less than 100mV/dec subthreshold slope.

Extremely thin SOI (ETSOI) technology: Past, present, and future

As the mainstream bulk devices face formidable challenges to scale beyond 20nm node, there is an increasingly renewed interest in fully depleted devices for continued CMOS scaling. In this paper, we provide an overview of extremely thin SOI (ETSOI), a viable fully depleted device architecture for future technology. Barriers that prevented ETSOI becoming a mainstream technology in the past are specified and solutions to overcome those barriers are provided.

Advanced gate stacks with fully silicided (FUSI) gates and high-/spl kappa/ dielectrics: enhanced performance at reduced gate leakage

The key result in this work is that FUSI/HfSi/sub x/O/sub y/ gate stacks offer both significant gate leakage reduction (due to high-/spl kappa/) and drive current improvement at T/sub inv/ /spl sim/ 2 nm (due to: (i) elimination of poly depletion effect, /spl sim/ 0.5 nm, and (ii) the high mobility of HfSi/sub x/O/sub y/). We also demonstrate that threshold voltage for both PFETs and NFETs can be adjusted from midgap to the values of Vt(PFET)/spl sim/ -0.4 V and Vt(NFET) /spl sim/ + 0.3 V by poly-Si predoping by implantation (Al or As) and FUSI alloying. Significantly improved charge trapping (V/sub t/ stability) was found in the case of NiSi/ HfSi/sub x/O/sub y/ compared to the same gate electrode with HfO/sub 2/ dielectric.

80 nm polysilicon gated n-FETs with ultra-thin Al/sub 2/O/sub 3/ gate dielectric for ULSI applications

This work demonstrates the integration of Al/sub 2/O/sub 3/ gate-dielectrics into a sub 0.1 /spl mu/m n-MOS process using polycrystalline silicon gates, Devices incorporating Al/sub 2/O/sub 3/ films with a dielectric constant /spl epsi/-11 and electrical thickness t/sub qm/<1.5 nm have been fabricated. Gate leakage currents are /spl sim/100 times lower than those found in SiO/sub 2/ films of equivalent thickness. Encouraging device characteristics are shown. Charging due to slow states and/or fixed charge have been shown to be in the 100 mV range which may be related to the somewhat reduced mobility. The room temperature reliability of these devices based upon the values of /spl beta/ (Weibull slope) and /spl gamma/ (voltage acceleration) suggest that the Al/sub 2/O/sub 3/ lifetime may exceed that of SiO/sub 2/ films.

High performance FDSOI CMOS technology with metal gate and high-k

A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.

Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications

Extremely thin SOI (ETSOI) MOSFET is a viable option for future CMOS scaling owing to superior short-channel control and immunity to random dopant fluctuation. However, challenges of ETSOI integration have so far hindered its adoption for mainstream CMOS. This is especially true for low-power applications, where SOI wafer cost is deemed to significantly add to the total cost. We have recently reported a novel integration scheme to overcome some of the major ETSOI manufacturing issues such as difficulty in doping thin silicon layer, process induced silicon loss, and the dilemma of reduction of external resistance and the increase of parasitic capacitance [1, 2]. The proposed integration flow significantly simplifies device processing and leads to considerable reduction in the number of critical masks [2].

CVD Co and its application to Cu damascene interconnections

Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by AFM) showed correlations with amounts of in-film oxygen/carbon. Cobalt diffused through copper at normal processing temperatures (by SIMS). CVD Co demonstrated diffusion barrier performance to Cu (by Triangular Voltage Sweep, TVS), but not to O2. CVD Co was applied to 32 nm/22 nm damascene Cu interconnect fabrication in a scheme defined by the material studies. Lower post-CMP defect density and longer electromigration lifetimes were obtained.