Lieve Teugels

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an L_G of 60 nm an extrinsic g_m of 1030 μS/μm at V_ds = 0.5 V is achieved which is a 1.75× increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to D_it resulting in an SS_SAT of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm L_G devices.

Experimental determination of the temperature dependence of the absolute rate coefficients of the HCCO + NO2 and HCCO + H2 reactions

The absolute rate coefficients of the gas-phase reactions HCCO+NO2 and HCCO+H2 were experimentally determined for the first time over extended temperature ranges: 293 K to 769 K and 438 K to 761 K, respectively. HCCO radicals were generated by pulsed-laser photolysis of CH2CO at 193 nm. Their subsequent decay, under pseudo-first-order conditions, was monitored in real-time using a laser-photofragment/laser-induced fluorescence technique. The rate coefficient of HCCO+NO2 exhibits a negative temperature dependence similar to that of the HCCO+NO reaction, but the Arrhenius A-factor is 1.4 times larger; k(T)(HCCO+NO2)=(2.3±0.4)×10−11 exp (340±40) K/T) cm3 s−1. It is argued that, if the major product channels yield N, NH or NCO, the HCCO+NO2 reaction should be a significant removal route of NOx in stationary combustion systems under fuel-rich conditions at temperatures below ca. 1300 K. The rate coefficient for the HCCO+H2 reaction was determined as k(T)(HCCO+H2)=(2.2±1.4)×10−11 exp(−2000±400)K/T). In fuel-rich combustion environments, given the high concentrations of H2, this reaction is likely to be a significant loss process for HCCO radicals: k(1500 K)HCCO+H2=(6+0.4−0.2)×10−12 cm−3 s−1, a factor of three greater than k(1500 K)HCCO+O2.

'A Strong Woman, Who Can Find?' a Study of Characterization in Genesis 24, With Some Perspectives On the General Presentation of Isaac and Rebekah in the Genesis Narratives

The portrayal of the patriarch Isaac in the pentateuchal narratives is, both quantitatively and qualitatively, meagre. Even when solutions are brought forward as to the quanti tative aspect, the weak picture of Isaac remains problematic. A narrative analysis, focused on characterization in Gen. 24, shows that Rebekah, however, is presented as a strong woman. In the paper the suggestion is offered that the contrasting presenta tion of the two characters fits their particular task in the Isaac-Rebekah narratives: Isaac is the passive bearer of the blessing, while Rebekah is the active, divinely-led helper, that assists him in keeping and passing the blessing on to the right sucessor.

Improving defectivity for III-V CMP processes for <10 nm technology nodes

III-V high mobility channel materials are being considered for advanced devices beyond the 10 nm technology node. For pMOS devices, Ge and SiGe have already been shown to be viable candidates [1,2] while for nMOS devices our focus lies on III-V materials such as InP and InGaAs. For the integration of III-V channel materials, several approaches are being explored: the aspect ratio trapping (ART) method and hetero-epitaxy of III-V compound semiconductors on blanket Si using strain-relaxed buffer layers. This paper focuses on reducing the defectivity of the III-V layers during CMP steps needed for either approach. We show that the use of an improved pad/slurry combination can significantly reduce the CMP-induced damage to the InP fins in the ART approach and can achieve a post-CMP roughness r.m.s. of InGaAs SRB layers of ~0.7 nm.

CMP on SiGe materials — Linking chemical and physical properties to design low defect and selective slurries

Germanium as a high electron mobility material (HEMM) is considered to replace silicon in FET devices. However, since a lot of technical challenges for pure germanium still need to be overcome, Silicon-Germanium alloys (SiGe) devices combine properties of Silicon and Germanium almost linear depending on their composition and are easier to integrate. For p-MOS integration schemes, SiGe has shown to be a promising candidate [1]. Furthermore, Si1-xGex materials are used as strain relaxed buffer for Ge p-MOS devices. This paper shows on the one hand SiGe stochiometry dependent properties which are important during a CMP process e.g. etching rates and on the other hand demonstrates the latest developments of CMP slurries and their performance for such alloys. We show that slurries containing germanium enhancers and Poly-Si suppressors showed improved defect performance and excellent selectivities towards different substrates as eHarp and Poly-Si.

Contact module at dense gate pitch technology challenges

In this paper we elaborate on challenges faced by contact formation at dense pitch: maintaining gate-to-contact reliability and keeping contact resistance low. We investigate intrinsic and integrated reliability of the gate-to-contact spacing materials and demonstrate capability of nitride gate encapsulation combined with a self-aligned contact etch process to handle misaligned contacts. Resistance of a silicide-through contact process is evaluated on fin substrates.

The Anonymous Matchmaker: an Enquiry Into the Characterization of the Servant of Abraham in Genesis 24

The servant of Abraham is the protagonist in Gen. 24. His characterization, however, only focuses on his role as a mediator. First, by the balanced use of appellations, he is depicted at the same time as an anonymous servant and as the full representative of Abraham. Secondly, by his speech, his main character indicator, he appears as a very clever man. By these features the servant receives a specific task in the overall plan of Gen. 24. Whereas Isaac is the incarnation of the divine promise and Rebekah is the divinely-sent helper, the servant is the incarnation of the divine guidance.

In Depth Analysis of 3D NAND Enablers in Gate Stack Integration and Demonstration in 3D Devices

An in-depth analysis of gate stack enhancements that enable multi-Gb 3D NAND products is performed. Alternative charge trapping layer, enhanced tunnel oxide based on the VariOT concept and metal gate with Al2O3 high-k liner have been proposed and evaluated. The most promising solutions were successfully integrated in 3D devices. Integration challenges of the replacement gate approach, required to have metal gate in 3D NAND, are also analyzed and discussed in detail.