Patrick W. DeHaven

Metallization by plating for high-performance multichip modules

Electrolytic plating is used to produce the interconnect wiring on the current generation of high-performance multichip modules used in IBM S/390® and AS/400® servers. This paper reviews the material and manufacturing requirements for successful implementation of a multilayer high-density wiring pattern involving electroplated copper metal and polyimide dielectric. Various strategies for the construction of thin-film structures (planarized and nonplanarized) are outlined, and the advantages of electrolytic plating over dry deposition techniques are described.

FDSOI radiation dosimeters

We describe the fabrication of radiation dosimeters utilizing fully-depleted silicon-on insulator (FDSOI) substrates, and further demonstrate the detection of various ionizing radiation types including protons, a-particles, and X-rays by the threshold voltage (Vth) changes caused by the radiation-induced charge trapped in the buried oxide. Our FDSOI dosimeter exhibits a sensitivity of ∼3mV/krad(SiO2) to 1MeV protons and ∼10mV/krad(SiO2) to 8keV X-rays, respectively. The comparison of FDSOI dosimeter with existing bulk-Si detectors shows comparable sensitivity, with the additional advantage of up to 90 days of BOX charge retention time. Our findings are encouraging and provide innovative implementation of SOI technology in microelectronics radiation dosimetry while maintaining CMOS process compatibility.

Implementation of Robust Nickel Alloy Salicide Process for High-Performance 65nm SOI CMOS Manufacturing

Addition of Pt to Ni silicide produces a robust [NixPt(1-x)]Si, which shows an improved morphological stability, an important reduction in encroachment defect density, a reduced tendency to form NiSi2 and significant variations in monosilicide texture without degrading the device performance or the yield of high-performance 65 nm SOI technologies.

Structural and Chemical Characterization of Tungsten Gate Stack for 1 Gb Dram

Material interaction during integration of tungsten gate stack for 1 Gb DRAM was investigated by Transition Electron Microscopy (TEM), X-ray Diffraction analysis (XRD) and Auger Electron Spectroscopy (AES). During selective side-wall oxidation tungsten gate conductor undergoes a structural transformation. The transformation results in the reduction of tungsten crystal lattice spacing, re-crystallization of tungsten and/or growth of grains. During a highly selective oxidation process, a relatively small but noticeable amount of oxygen was incorporated into the tungsten layer. The incorporation of oxygen is attributed to the formation of a stable WO x (x

In-Situ Study of Ti/TiN Stability under Nitrogen Anneal

The effectiveness of a TiN capping layer to prevent the conversion of α-titantium to titanium nitride when annealed in a nitrogen ambient has been studied over the temperature range 300–700°C using in-situ high temperature diffraction and transmission electron microscopy. Over the time range of interest (four hours), no evidence of Ti reaction was observed at 300°C. At 450°C. nitrogen was found to diffuse into the Ti to form a Ti(N) solid solution. Above 500°C the titanium is transformed to a second phase: however this reaction follows two different kinetic paths, depending on the annealing temperature. Below 600°C. the reaction proceeds in two stages, with the first stage consisting of Ti(N) formation, and the second stage consisting of the conversion of the Ti(N) with a transformation mechanism characteristic of short range diffusion (grain edge nucleation). Above 600°C, a simple linear transformation rate is observed.