Qingyun Yang

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.

Understanding mobility mechanisms in extremely scaled HfO 2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and V t -tuning dipoles with gate-first process

We demonstrate a novel “remote interfacial layer (IL) scavenging” technique yielding a record-setting equivalent oxide thickness (EOT) of 0.42 nm using a HfO2-based MOSFET high-к gate dielectric. Intrinsic effects of IL scaling on carrier mobility are clarified using this method. We reveal that the mobility degradation observed for La-containing high-к is not due to the La dipole but due to the intrinsic IL scaling effect, whereas an Al dipole brings about additional mobility degradation. This unique nature of the La dipole enables aggressive EOT scaling in conjunction with IL scaling for the 16 nm technology node without extrinsic mobility degradation.

A high-speed, high-sensitivity silicon lateral trench photodetector

We report a novel silicon lateral trench photodetector that decouples the carrier transit distance from the light absorption depth, enabling both high speed and high responsivity. The photodetector, fabricated with fully VLSI compatible processes, exhibits a 6-dB bandwidth of 1.5 GHz at 3.0 V and an external quantum efficiency of 68% at 845 nm wavelength. A photoreceiver with a wire-bonded lateral trench detector and a BiCMOS transimpedance amplifier demonstrates excellent operation at 2.5 Gb/s data rate and 845 nm wavelength with only a 3.3 V bias.

Characterization of linewidth variation on 248- and 193-nm exposure tools

The line-width variation of a 193 nm lithographic process utilizing a 0.60 NA scanner and a binary reticle is compared to that of a 248 nm lithographic processes utilizing a 0.68 NA scanner and a variety of reticle technologies. These include binary, attenuated PSM with assist features and alternating PSM reticles. Despite the fact that the 193 nm tool has a lower NA and that the data was generated using a binary reticle, the 193 nm lithographic process allows for the line-width values to be pushed lower than previously achieved with 248 nm lithographic processes. The 3-sigma values from 4000 electrical line-width measurements per wafer (160 measurements per 25*25 mm field, 25 fields per wafer) were calculated for different mask features. The 193 nm process was capable of reaching line-widths needed for future generations of advance logic chips. Compared to the 193 nm process utilizing a binary reticle, only the 248 nm processes utilizing either an attenuated PSM with assist features or an alternating PSM reticle had similarly low line-width variation. The 248 nm processes utilizing a binary reticle had higher line-width variation even at larger poly gate conductor line-widths.