Rafael Venegas

Investigation of PECVD dielectrics for nondispersive metal-insulator-metal capacitors

Metal-insulator-metal (MIM) capacitors with PECVD nitride exhibit trap-induced dispersive behavior, which leads to degradation in capacitor linearity at low frequencies, limiting the accuracy in precision analog circuits. While LPCVD oxide results in nondispersive behavior, the high deposition temperature excludes the use of LPCVD dielectrics for MIM capacitors using the standard back-end metal layers as capacitor bottom plates. The latter is preferred in view of the low substrate coupling needed for RF applications. In this work, alternative PECVD dielectrics have been investigated with respect to frequency dependence of voltage linearity, hysteresis, matching, and leakage characteristics. It will be shown that ONO stacks offer a combination of good voltage linearity, absence of dispersive behavior and hysteresis, excellent matching, and low leakage.

Fabrication and Performance of Au-Free AlGaN/GaN-on-Silicon Power Devices With

Au-free GaN-based metal-insulator-semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al₂O₃-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si₃N₄ and Al₂O₃. The Si₃N₄ layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al₂O₃ layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600 V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <;1 Ω·mm. The devices show high maximum output current density (>0.4 A/mm); and low gate and drain leakage (<;10^-10 A/mm). The maximum pulsed mode drain-source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m Ω·cm².

{\rm Al}_{2}{\rm O}_{3}

An in-depth analysis of the impact of hot-carrier stress (HCS) and oxide breakdown on 90 nm RFCMOS at low power bias is presented. Analog devices are found to be highly vulnerable to HCS under this condition. The post-breakdown MOSFET RF characteristics are completely explained by considering the location and the resistor-like behavior of the breakdown path.

and

In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver ~4 A at 2 V and show a median leakage of 1.3 μA at 25 °C and 3.8 μA at 150 °C measured at a reverse voltage of -200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing (LAC) and the length of field plate. We observed a saturated BV of ~600 V for the GET-SBDs with LAC larger than 5 μm. The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 μm-thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 μm) and remains at a value of ~10 nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.

{\rm Si}_{3}{\rm N}_{4}/{\rm Al}_{2}{\rm O}_{3}

In this paper we describe a novel fully self-aligned HBT architecture, which enables a maximum reduction of device parasitics. TCAD simulations show that this architecture is capable of achieving fT/fmax values of 295/425 GHz for an effective emitter area of 0.13times5 mum2. In this new process approach, which is fully CMOS compatible, the collector and base are grown in a single-step non-selective epitaxial process on top of pre-defined bipolar areas. This provides new opportunities for collector-base profile engineering. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial pedestal defines the intrinsic device and makes deep trench isolation redundant. We describe the major features of the integration scheme and show measured fT/fmax values of 300/220 GHz on the first fabricated devices with an effective emitter area of 0.13times5 mum2.

Gate Dielectrics

This paper presents a combined technique of high voltage off-state stress and current transient measurements to investigate the trapping/de-trapping characteristics of Au-free AlGaN/GaN Schottky barrier diodes. The device features a symmetric three-terminal structure with a central anode contact surrounded by two separate cathodes. Under the diode off-state stress conditions, the two separate cathodes were electrically shorted. The de-trapping dynamics was studied by monitoring the recovery of the two-dimensional electron gas (2DEG) current at different temperatures by applying 0.5 V at cathode 2 while grounding cathode 1. During the recovery, the anode contact acts as a sensor of changes in diode leakage current. This leakage variation was found to be mainly due to the barrier height variation. With this method, the energy level and capture cross section of different traps in the AlGaN/GaN Schottky barrier diode can be extracted. Furthermore, the physical location of different trapping phenomena is indic...

RF performance vulnerability to hot carrier stress and consequent breakdown in low power 90 nm RFCMOS

An improved fully self-aligned SiGe:C HBT architecture featuring a single-step epitaxial collector-base process is described. An fMAX value of 400GHz is reached by structural as well as intrinsic advancements made to the HBT device.

Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode With Gated Edge Termination on 200-mm Silicon Substrate

SiGe heterojunction bipolar transistors (HBTs) are usually optimized to obtain best performance in the forward operation mode. In this paper, we demonstrate that a simultaneous excellent performance in the reverse mode of operation can be obtained as well. A fT / fmax combination of 50/100 GHz is obtained, which is, to our knowledge, the best value reported for a Si-based HBT operating in the reverse mode. This excellent performance is analyzed and explained by studying the different delay components of the device in the reverse operation mode. It is shown that the extrinsic SiGe base region plays a crucial role. Additionally, good low-power performance in the reverse operation mode is obtained as well, which is attributed to a reduction in the device parasitic contributions. The simultaneous availability of a high-speed performance in the forward mode and a low-power performance in the reverse mode offers additional flexibility to optimize circuit performance in terms of speed, power, and area.

A Novel Fully Self-Aligned SiGe:C HBT Architecture Featuring a Single-Step Epitaxial Collector-Base Process

In this paper a measurement methodology, using a two-dimensional electron gas (2DEG) resistor, is used to evaluate the dispersion of three different type of buffers, namely a step graded buffer, a buffer with low temperature (LT) AlN interlayers and a superlattice buffer. Together with a dedicated Design of Experiments (DOE), these measurements allowed us to identify the physical origin of the dispersion and identify the key parts of the buffer which influence the buffer-induced dispersion of the 2DEG.

Current transient spectroscopy for trapping analysis on Au-free AlGaN/GaN Schottky barrier diode

Dynamic characterization (Pulsed I–V) on Au-free AlGaN/GaN Schottky Barrier Diodes (SBDs) has been performed to evaluate the impact of negative quiescent biases on the forward characteristics. Results show an increase of on-resistance when more negative quiescent biases are applied, and a sudden current collapse phenomenon when the quiescent bias exceeds 175 V. Furthermore, the measurements show a common signature: the total current collapse is the result of the trapping phenomena occurring around the Schottky contact corner. The trap levels of 0.5 eV and 1.0 eV have been characterized from current transient spectroscopy. A TCAD model with these two trap levels as donor states at the Si3N4/AlGaN interface has been defined, to understand their role and explain the observed behavior of AlGaN/GaN SBDs from this dynamic measurement. We propose that trapping at deep energy levels (Trap1 = 1.0 eV), existing at the Si3N4/AlGaN interface, is responsible for the gradual current reduction observed for negative quiescent biases up to Anode-to-Cathode voltage (VAC )o f175 V. The electron filling at the shallower traps with high density at energy level located 0.5 eV starts at higher reverse biases, resulting in a strong Fermi-level pinning, which can be the cause of sudden current collapse. 2014 Published by Elsevier Ltd.