Robert C. Wong

SRAM cell design for stability methodology

SRAM stability during word line disturb (access disturb) is becoming a key constraint for V/sub DD/ scaling (Burnett, 1994). In this paper we present a design methodology for SRAM stability during access disturb. In this methodology, the SRAM access disturb margin (ADM) is defined as the ratio of the magnitude of the critical current to maintain SRAM stability (I/sub CRIT/) to the sigma of I/sub CRIT/. Using ADM as a figure of merit, this methodology enables one to project the cell stability margin due to process variations, e.g. V/sub T/ variation, during design of a SRAM cell. Using statistical analysis, the required stability margin for an application requirement such as array size and available redundancy can be estimated. Direct cell probing and array test can be used to verify that the stability target is met.

Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology

Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single chip - high performance, low leakage and mixed-signal components - is crucial. In this paper, we present the successful integration of a low leakage gate-dielectric using a triple-gate-oxide process with 16 /spl Aring//24 /spl Aring//52 /spl Aring/ layers, a low-k BEOL and mixed signal components. The 1.5 V SRAM cell with a footprint of 1.26 /spl mu/m/sup 2/ is the smallest 1.5 V cell reported.

Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction

We propose an efficient physics-based mixed-mode statistical simulation methodology for nanoscale devices and circuits. Here, 3-D Technology Computer Aided Design models pose a barrier for efficient simulation of variability as they generally involve millions of nodes in their mesh representations. The proposed methodology, which has been implemented for FinFET/tri-gate static random access memory (SRAM) design, overcomes this barrier by leveraging advanced physics-based 2-D (P2-D) devices with optimized meshes that are derived from 3-D FinFET models with tuned device parasitics. This enables physics-based simulation as well as physics-based variability input parameters. To improve accuracy, an embedded automated flow enables extraction of all external nodal parasitics, directly from a 3-D FinFET circuit layout representation. The circuits consisting of advanced P2-D devices are then back annotated with the nodal parasitics to enable fast and accurate SRAM dynamic margin mixed-mode simulations. Results demonstrate up to 200× speedup compared with traditional 3-D device simulations, and around five orders of magnitude wall clock time improvement on account of fast statistical methodologies, which are superior in comparison with traditional Monte Carlo analysis. This makes it feasible to supplant often inaccurate compact model-based simulations by true mixed-mode device simulations in statistical engines. The proposed physics-based methodology is also shown to corroborate well with hardware measurements.

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased Weff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at Lg=12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Product Burn-in Stress Impacts on SRAM Array Performance

Product burn-in stresses are commonly performed on SRAM array to accelerate transistor failure mechanism and screen out weak SRAM cells. For sub-100 nm technology, the possible impacts from burn-in stress are negative bias temperature instability (NBTI) (Schroder and Babcock, 2003) on PFET and hot carrier effect (HCE) on NFET. Recently several groups (Muller et al., 2004 and LaRosa et al., 2006) reported the studies of NBTI impact on SRAM array performance, either using circuit simulation (Muller et al., 2004) or based on test results of discrete SRAM cell (LaRosa et al., 2006). Our study, for the first time, is directly based on the product results from burn-in stress on SRAM array. With device reliability models and circuit simulation, we analyzed the shift of key product parameters: SRAM array stand-by current (Iddq) and minimum array operation voltage (Vcsmin). Our studies show that PFET NBTI is the dominant factor that is responsible for the degradation of SRAM array stability, and its impact on Vcsmin is predictable by Iddq data and modeling.

Tristate Inverter Array: A New Technology Development Yield Learning Vehicle Complementing Traditional SRAM Arrays

The SRAM bitcell array has been traditionally used as a yield learning vehicle for new technologies. However, the yield of the SRAM bitcell is susceptible to parametric variations and subtle process defects/variations. In this paper, a new functional array called the tristated inverter array is discussed which is much less susceptible to both parametric variation and subtle process defects while retaining all the useful features of the SRAM array (fail mappability, ease of isolation of fails, regular design). This structure can be used very effectively in yield learning as a complimentary test structure to the SRAM array for learning hard process defects.

Direct SRAM Operation Margin Computation with Random Skews of Device Characteristics

SRAM has been generally characterized with some SNM [12] from the voltage–voltage (VV) plots or the Icrit from the current–voltage (IV) plots. They do indicate the robustness of the SRAM operations but would not provide sufficient information for SRAM designers, as to the possible SRAM yield and the redundancy requirements. One way to estimate SRAM yield is based on the expected fail count with the Poisson distribution

A novel sram cell design to improve stability

{\hbox{YIELD}} = \sum\limits_{n = 0}^k {\tfrac{{{\lambda^n}\exp ( - \lambda )}}{{n!}}}