Robert Lo

How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?

Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very difficult since thin wafers lose the supporting strength. Usually, the thin wafer is attached to a supporting wafer with adhesive to increase its rigidity and bending stiffness. Thus, adhesive is the key enabling material for thin-wafer handling, and how to select adhesive materials for temporary bonding and de-bonding is the focus in this study. Two sizes of wafers are considered; the 200mm wafers are used to find out the important and unimportant parameters in selecting the adhesive and then apply them to the 300mm wafers. It will be shown that wafer thinning and PECVD (plasma enhanced chemical vapor deposition) in vacuum chamber are the two critical steps for thin-wafer handling. The 300mm wafers are thinned down to 50μm and evaluated in different structures including: (a) blanket wafers, (b) wafers with 80μm solder bumps, and (c) wafers with 20μm micro-bumps and TSVs in 10μm diameter and 40∼50μm pitch. Based on this study, a set of useful process guidelines and recommendations is provided.

Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking

In this study, we used a chip-on-chip test vehicle with 30μm pitch lead-free solder micro bump to study the electromigration reliability of solder micro bump interconnection used for 3D chip stacking. The structure of micro bump composed of Sn2.5Ag solder material with Cu/Ni under bump metallization (UBM) was selected. Two types of interconnection were chosen to evaluate the effect of the joint structure on electromigration behavior. The type I was the chip stacking sample with the IMC / Sn (5 um thick) / IMC joint structure, while the type II was the sample with fully transformed Ni3Sn4 intermetallic (IMC) joints made by the post-treatment of long time thermal aging. Electromigration test was performed on the four point Kelvin structure and daisy-chain structure under the current stressing of 104∼105 A/cm2 at an ambient temperature of 150°C. During the electromigration test, the resistance increase was in-situ monitored to determine the definite time to failure. The microstructure evolution was also examined at different stages of joint resistance increase. From the testing results, the rapid increase of joint resistance was found at the early stage under current stressing in the type I micro bump. After that, the joint resistance increase became slower. This mild increasing stage was much longer than the early stage. For the type II sample, however, the resistance increasing rate was quiet lower than that of the type I sample at the identical testing time. With a higher current density in the order of 105 A/cm2 in the micro joint, the effect of joule heating caused the damage happened in Al trace and Cu UBM while the residual Sn solder had been transformed to be Ni3Sn4 IMC totally and few voids were found around IMC by the microstructure observation. When applied a current density in the order of 104 A/cm2 on the micro joint, the residual Sn was also fully transformed to be IMC. However, the failure mode of the micro joint is not clear yet because the experiments are still on-going. The resistance variation is showing a steady state under such a condition of current stressing and so far no open failure happened.

Characterization and reliability assessment of solder microbumps and assembly for 3D IC integration

In this investigation, Cu/Sn lead-free solder microbumps with 10μm pads on 20μm pitch are designed and fabricated. The chip size is 5mm × 5mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. With the current process, the undercut is less than 1μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder micro bumped chip is bonded on a Si wafer (chip-to-wafer or C2W bonding). Furthermore, the micro-gap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips w/o underfill is measured and exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, SAT analysis, and cross-section with SEM analysis. The stacked ICs are evaluated by reliability tests, including thermal cycling test (−55⇆125°C, dwell and ramp times = 15 min). Finally, ultra find-pitch (5μm pads on 10μm pitch) lead-free solder microbumping is explored.

Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization

3D IC integration can be accomplished by using the approaches such as chip-on-chip, chip-on-wafer and wafer-on-wafer integration. The scheme of chip-on-chip shows the advantages of high flexibility and yield during assembly process. However, low fabrication throughput has been a major issue. When compared to chip-on-chip integrations, wafer-on-wafer may provide the higher manufacturing throughput but its overall yield will be limited by accumulative yield. Also, good chips are forced to bond on bad chip. Therefore, the development of chip-on-wafer integration may be a better scheme for 3D chip stacking. In this study, a high-yield and fluxless chip-on-wafer bonding process with 30μm pitch lead-free solder micro bump interconnection were demonstrated and the reliability of micro joint was also evaluated. Test chip adopted in this study had more than 3000 micro bumps with a diameter of 18μm and a pitch of 30μm. Sn2.5Ag solder material was electroplated on Cu/Ni under bump metallurgy (UBM) of both the test chip and 200mm wafer. To achieve the purpose of fluxless chip-on-wafer bonding, the plasma pre-treatment was applied to both the test chips and bonded wafer. The thermo-compression bonding method with the gap control capability was also carried out. In this work, the fluxless thermo-compression bonding having more than 90% CoW yield had been accomplished. The factor of Sn thickness was found to evidently influence the CoW yield. With the optimized plasma treatment parameters and bonding conditions, a well-aligned and robust joining of micro bump without using flux could be obtained. The results of reliability test revealed that the introduction of underfill could apparently enhance the reliability performance of micro joint under mechanical evaluation. Also, the solder micro bump joint showed excellent electromigration resistance when compared to standard flip chip bump under current stress of 5×10−4 A/cm2 at an ambient temperature of 150°C.

Wafer Bumping, Assembly, and Reliability of Fine-Pitch Lead-Free Micro Solder Joints for 3-D IC Integration

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored.

Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP

In this study, a 3D IC integration system-in-package (SiP) with TSV/RDL/IPD interposer is designed and developed. Emphasis is placed on the Cu revealing, embedded stress sensors, non-destructive inspection, thermal modeling and measurement, and final assembly and reliability assessments.

Identification of Mechanical Properties of Intermetallic Compounds on Lead Free Solder

In this paper, we present methods for obtaining mechanical properties of silicon substrates and two intermetallic compounds (IMC) formed at the interfaces between lead-free solders and the copper and between leadfree solders and nickel substrates. To determine the mechanical properties of the silicon substrate, 255 um (100) and 306 um (110) thick silicon wafers were adopted. With proper sensor locations of strain gages and ANSYS finite element models, the in-plane Young’s moduli were optimally determined to be E = 101.6 GPa, E =140.7 GPa, E = 140.5 GPa, which agreed with the trend of theoretical values in each orientation. Some defects made the Young’s moduli smaller than the theoretical values. Further, the in-plane Young’s moduli of the anisotropic (110) wafer were inversely determined to be E = 170.1 GPa, E =157.9 GPa, which were also smaller but closer to the theoretical values because of its thicker thickness. For IMC material properties, two types of lead free solder were used, namely, SnZn and Sn. For the IMC mechanical property determination using SnZn solder, specimens were prepared by dipping to overcome the poor wetting problem. A uniform layer of Cu33.5Zn66.5 IMC was then formed. For out-ofplane Young’s modulus measurement, the specimen was pressed by a nanoindentor. An average value for the Young’s modulus was recorded to be 158 GPa. With the whole field slope measurement method, the reflection moire, the CTE of Cu33.4Zn66.5 was found to be approximate to that of copper. As for the Cu-Sn intermetallic compounds, electroplating was used to have an even tin layer on copper substrates. After soldering reaction and annealing, there existed two phases of Cu-Sn IMC, Cu6Sn5 and Cu3Sn. With the nanoindentor, average values for the Young’s moduli were determined to be 124 GPa for Cu6Sn5 and 143 GPa for Cu3Sn. The warpage change of Cu3Sn/copper foil structure under thermal load is adopted for the CTE of Cu3Sn, which is determined to be 18.2 ppm/C. Furthermore, nickel substrate electroplated with tin was adopted for Ni3Sn4 IMC, whose Young’s modulus was determined to be 152 GPa with nanoindentation.

Nonlinear thermal stress analyses and design guidelines for through silicon vias (TSVs) in 3D IC integration

In this investigation, a set of empirical equations which predicts the maximum thermal stresses at the vicinity of a copper filled TSV for 3D IC integration has been proposed. The finite element model of a symmetrical single in-line TSV with redistribution layer has been created at first and the parametric study includes the TSV diameter, pitch, and thickness, and the thickness of SiO2 passivation and Cu seed layer. The methodology of design of experiments (DOE) has been adopted to deliver a set of empirical equations which captures the most important mechanical parameters of TSVs to comprehend the corresponding thermal stress and strain responses. Through this set of empirical equations, the estimated maximum thermal stresses and strains for different TSV diameter (from 10μm to 50μm) can be explained and the significant geometrical parameters can be easily observed. In addition, based on the present parametric study and results, a set of design guidelines for optimizing the mechanical performance of copper filled TSV in 3D IC integration has been proposed. These results are helpful to engineers if thermal stress solutions for TSVs in 3D IC integration are required.

Wafer bumping, assembly, and reliability assessment of μbumps with 5μm pads on 10μm pitch for 3D IC integration

In this study, ultra fine pitch Cu/Sn lead-free solder microbumps are investigated. Emphasis is placed on wafer bumping, assembly, and reliability of microbumps for 3D IC integration applications. The test vehicle consists of a chip (5mm × 5mm) with 3,200 pads. The pad size is 5μm in diameter and on 10μm pitch. A daisy-chain feature is adopted for the characterization and reliability Assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. The wet-etching process is used for the etching of seed layer. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but still achieve good plating uniformity. In addition, the shear test has been adopted to characterize the bump strength, which exceeds the specification. After wafer bumping and characterization of the microbumps, the Moores law wafer is dicing into individual chips for chip-to-chip (C2C) bonding of the micro solder joints. The C2C bonding is a flux thermocompression process with a peak temperature of 260°C. The microstructure analyses reveal that the ultra fine pitch micro solder joint can be considered as an intermetallic compound (IMC) joint composed of Cu6Sn5 and a few residual solder compounds.

Characterization of thin films and intermetallic compounds in solder joint

Numerical simulation such as finite element methods have been widespread in structure designs and analyses in IC industry and researches. Only if the inputs of material properties are correct, can the outcome be referable to its applications. Thin-film materials have been widely used in many applications. The mechanical properties of thin films may be markedly distinct with different processes and processing conditions. To study the mechanical behaviour of thin films, thin films on substrates are adopted most often [Jie-Hua Zhao, Yong Du, Michael Morgen, and Paul S. Ho, [200]]. The most commonly used material for substrate is silicon, which has low coefficient of thermal expansion (CTE) and is a prevalent semiconductor material. The theoretical values of Youngs moduli of silicon were usually applied. However, the values might be different in practice. Before further study of thin-films, the actual mechanical properties of silicon substrates should be cautiously investigated first. Intermetallic compounds (IMC) are formed when interconnections in IC packages are jointed with solder. Though IMC just comes into a small amount, it usually dominates the reliability of the interconnections because of its characteristic material properties. Individual mechanical properties of a solder/IMC/UBM layered structure are required for simulation and analyses of the interconnection reliability, but always difficult to obtain because the thickness of each layer is on micrometer order. Further, it is impossible to separate each thin layer and apply commercially available testing machines to test it.