Robin Cheung

Multi-level Step and Flash Imprint Lithography for Direct Patterning of Dielectrics

The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.

Influence of plating parameters on reliability of copper metallization

This work investigates the impact of plating parameters on the physical and electrical properties of plated copper films. Process parameters such as the plating current density and wafer rotation speed are known to affect the grain size and the residual stress in plated Cu films. We correlate the process parameters with trapped contamination in the films, which in turn influences the pre/post-anneal grain size and the relaxation of the residual stress. Preliminary reliability measurements show that the longevity of the interconnect structure is dependent on the intrinsic properties of the plated copper.

Device design for global shutter operation in a 1.1-μm pixel image sensor and its application to near infrared sensing

Global shutter is a feature of some CMOS image sensors that allows capture of an entire image at a single point in time. We discuss how the device architecture of InVisage’s QuantumFilm enables global shutter operation by controlling the bias on the device stack without an additional transistor, giving high shutter efficiency in a 1.1 μm pixel CMOS image sensor. We use drift-diffusion device simulations to inform our design and reveal device and material properties that are key for carrier selectivity. Based on our device model, we fabricated global-shutter-enabled QuantumFilm devices for near infrared sensing applications and present a characterization of our devices.

Extension of copper plating to 0.13 /spl mu/m nodes by pulse-modulated plating

The electro-chemical deposition of copper can carried out by normal DC plating or using pulse plating approach. The superfill for gap fill can be achieved using either of these approaches-DC plating or pulse plating. The pulse plating approach has been observed to show advantages of greater tolerance to seed layer morphology besides controlled planarity, with no major detrimental effects on electrical yield or other film properties.