Rode R. Mora

CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)

Perfectly self aligned vertical multiple independent gate field effect transistor (MIGFET) CMOS devices have been fabricated. The unique process used to fabricate these devices allow them to be integrated with FinFET devices. Device and circuit simulations have been used to explain the device and explore new applications using this device. A novel application of the MIGFET as a signal mixer has been demonstrated. The undoped channel, very thin body, perfectly matched gates allows charge coupling of the two signals and provide a new family of applications using the MIGFET mixer. Since the process allows integration of regular CMOS double gate devices and MIGFET devices this technology has potential for various digital and analog mixed-signal applications.

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2µm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30µm length the stress is 45% greater compared to the case of 7µm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.

Fabrication and operation of sub-50 nm strained-Si on Si/sub 1-x/Ge/sub x/ Insulator (SGOI) CMOSFETs

First functional 45 nm SGOI CMOS devices on bonded SGOI substrates with T/sub SOI/<45 nm exhibited superior short-channel control and comparable reliability to SOI devices. A 67% Gm enhancement was observed in long-channel nMOS SGOI devices, 18% drive current increase for short-channel SGOI devices, and 12% faster ring-oscillators were exhibited with respect to control SOI devices. Functional SRAM bit cells down to V/sub dd/=0.9 V were also demonstrated.