Karla Romero

A novel approach for the patterning and high-volume production of sub-40-nm gates

A novel approach for the patterning and manufacturing of sub-40-nm gate structures is presented. Rather than using resist or an inorganic hardmask as the patterning layer, this gate patterning scheme uses an amorphous carbon (a:C) and cap hardmask to pattern small gates. Healthy and manufacturable gate lengths have been achieved below 35 nm with this scheme, and the potential exists for further extendibility.

Minimizing poly end cap pull back by application of DFM and advanced etch approaches for 65nm and 45 nm technologies

As feature sizes decrease and the overall design shrinks, it is becoming increasingly difficult to reliably pattern gate line ends, or poly end caps, so that they are able to extend over to the field area without bridging into an adjacent feature. Furthermore, the trimming of the lines during the gate etch process is necessary due to the desire to decrease the poly length. However, the line end is also trimmed while trimming the gate sidewall, often at higher rates than the sidewall itself. This investigation focuses on decreasing the poly line end pullback, defined as the tip of the gate past active, using lithography techniques and advanced etch approaches for the 65 nm and 45 nm nodes.

CD analysis of advanced photolithography and its impact on critical design structures

SRAM stability has been an important topic for the high performance microprocessor industry. There are a several reasons why SRAMs are most susceptible to both process-induced variations and electrical parameter variability. Because the cache cells use devices with minimum gate lengths and widths, process variations become more severe. Sense amplifiers employ matched transistor pairs that are very sensitive to any process variation. This paper focuses on the patterning accuracy of minimum cell devices and of transistors that are meant to be matched. We used and correlated inline CD data, electrical data and lithographic simulations to measure the patterning fidelity of matched pairs. A small cache with failing matched pairs was chosen for the inline CD measurements. The measurements were done on wafers exposed on several scanners to identify their impact on matched pairs. Electrical measurements at especially designed addressable structures were done to verify the inline data. We analyzed the effect of dummy poly and varying line pitches as well as the active width impact on matched pair performance. Based on simulations, a sensitivity analysis for the analyzed layout portion to individual Zernike terms was done. Simulation results are compared with experimental data. Conclusions for the future design of matched transistor pairs and for scanner lens specifications will be given.