Shigehiro Kuge

SOI-DRAM circuit technologies for low power high speed multigiga scale memories

This paper describes a silicon on insulator (SOI) DRAM which has a body bias controlling technique for high-speed circuit operation and a new type of redundancy for low standby power operation, aimed at high yield. The body bias controlling technique contributes to super-body synchronous sensing and body-bias controlled logic. The super-body synchronous sensing achieves 3.0 ns faster sensing than body synchronous sensing and the body-bias controlled logic realizes 8.0 ns faster peripheral logic operation compared with a conventional logic scheme, at 1.5 V in a 4 Gb-level SOI DRAM. The body-bias controlled logic also realizes a body-bias change current reduction of 1/20, compared with a bulk well-structure. A new type of redundancy that overcomes the standby current failure resulting from a wordline-bitline short is also discussed in respect of yield and area penalty.

A 0.18 /spl mu/m 256 Mb DDR-SDRAM with low-cost post-mold-tuning method for DLL replica

A 200-MHz double-data-rate synchronous-DRAM (DDR-SDRAM) was developed. The chip contains a delay-locked loop (DLL) which performs over a wide range of operating conditions. Post-mold-tuning allows precise replica programming. A 200-MHz intra-chip data bus is suitable for DDR operation.

A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme

A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 V/sub cc/ bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75%.

SOI-DRAM circuit technologies for low power high speed multi-giga scale memories

New SOI-DRAM circuits were proposed and described. The body bias controlling technique, especially super body-synchronous sensing, is found to be suitable for low voltage operation. A new type of redundancy enables Icc2 reduction and promises high yield against the increasing standby current failure.

A 1.2 V to 3.3 V wide-voltage-range DRAM with 0.8 V array operation

DRAM arrays operating with power supply below 1 V, with stable sensing and high speed are required for multi-media systems. Reduction of data-retention current is also important. The authors present two data-retention current reduction techniques: charge-transfer pre-sensing scheme (CTPS) with 1/2Vcc bit-line precharge; and non-reset row block control (NRBC). An experimental 32 Mb DRAM using these techniques is fabricated in a 0.25 /spl mu/m triple-well CMOS technology.