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Dive into the research topics where Shinji Mori is active.

Publication


Featured researches published by Shinji Mori.


symposium on vlsi technology | 2007

Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

Nobuaki Yasutake; Atsushi Azuma; Tatsuya Ishida; Naoki Kusunoki; Shinji Mori; Hiroshi Itokawa; Ichiro Mizushima; Shintaro Okamoto; Tetsu Morooka; Nobutoshi Aoki; Shigeru Kawanaka; Satoshi Inaba; Y. Toyoshima

Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 muA/mum at Vdd=1.0 V, Ioff =100 nA/mum at 24 nm gate length, is demonstrated.


european solid-state device research conference | 2006

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

Nobuaki Yasutake; Tatsuya Ishida; Kazuya Ohuchi; Nobutoshi Aoki; Naoki Kusunoki; Shinji Mori; Ichiro Mizushima; Tetsu Morooka; K. Yahashi; Shigeru Kawanaka; K. Ishimaru; H. Ishiuchi

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe -source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved comparing with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451muA/mum at verbar;Vdd| of 0.9V, Ioff of 100 nA/mum (552 muA/mum at |Vdd | of 1.0V). Furthermore, by combining with Vdd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation


214th ECS Meeting | 2008

Influence of in-situ Boron Doping on the Surface Roughening of SiGe:B Films

Ryutaro Tsuchida; Shinji Mori; Tsutomu Sato; Naotaka Uchitomi; Ichiro Mizushima

Selective epitaxial growth of B-doped SiGe (SiGe:B) films is one of the key techniques for the embedded SiGe (e-SiGe) structure for high-performance pMOSFETs. Both the high Ge composition and the high B-doping concentration are desirable for increasing the stress in the channel region and decreasing the series resistance in the source/drain region. However, increasing Ge composition and B concentration may lead to defects in the epitaxial SiGe:B layer and thus to the roughening of the surface of the films. In this work, influence of B doping on the surface roughness and the roughening process in SiGe:B epitaxial films are examined.


Solid-state Electronics | 2007

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

Nobuaki Yasutake; Atsushi Azuma; Tatsuya Ishida; Kazuya Ohuchi; Nobutoshi Aoki; Naoki Kusunoki; Shinji Mori; Ichiro Mizushima; Tetsu Morooka; Shigeru Kawanaka; Y. Toyoshima


Archive | 2014

Nonvolatile semiconductor memory device and method of fabricating the same

Ichiro Mizushima; Yoshiaki Fukuzumi; Shinji Mori


Archive | 2012

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Shinji Mori


Archive | 2013

NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND FABRICATION METHOD THEREOF

Shinji Mori


international symposium on semiconductor manufacturing | 2007

Advanced surface cleanness evaluation technique using epitaxial silicon germanium (SiGe) process beyond 32nm node

Kaori Umezawa; Minako Inukai; Shinji Mori; Tsutomu Sato; I. Mizushima; Hiroshi Tomita; A. Yomoda


Archive | 2013

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD OF THE SAME

Shinji Mori; Jun Fujiki; Kiyotaka Miyano


Archive | 2012

Semiconductor memory device having a circuit formed on a single crystal semiconductor layer with varied germanium concentration

Yoshiaki Fukuzumi; Hideaki Aochi; Masaru Kito; Kiyotaka Miyano; Shinji Mori; Ichiro Mizushima

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