Tai-Yi Lee

Elimination of Floating body Effect and Thermal Instability in a Nano Quasi-SOI MOSFET with π-shaped Semiconductor Layer

In this paper, a new device structure called the quasi-SOI MOSFET with pi-shaped semiconductor conductive layer is proposed and demonstrated. In this structure, the pi-shaped source/drain layer is formed by the block oxide which consists of three separate oxide islands under the source, the drain, and the body regions, respectively. In other words, due to the three separate oxide islands forming two paths from source/drain to substrate, the generated holes and heat can be eliminated from this source/drain-tied scheme, thus, the proposed quasi-SOI structure shows to improve the kink effect and the self-heating problem as compared with that of conventional SOI structures. Moreover, owing to that the block oxide is utilized to restrict the electric field built between body and source/drain region, the ultra-short-channel effect is also diminished. Besides, our structure is based on the bulk wafer, thus, the cost can be cheaper than the SOI wafer

Investigation of the Novel Attributes of a Vertical MOSFET with Internal Block Layer (bVMOS): 2-D Simulation Study

In this paper, a vertical n-channel enhancement-type MOSFET with internal block layer (bVMOS) is investigated theoretically. In the proposed structure, the internal block layer comprises a buried block layer and a sidewall block layer. We also test three blocking materials (ex. doped Si, nitride and oxide) for performance comparisons. That is, the p-n junction region between the substrate and drain is isolated by the buried block layer thereby reducing the p-n junction leakage current and the parasitic capacitance. Similarly, the electrical field between the body and drain is blocked or shielded by the sidewall block layer; hence the intolerable ultra-short-channel effects, such as drain-induced barrier lowering (DIBL), hot-carrier effect, source/drain (S/D) punchthrough, and charge-sharing effect, are ameliorated tellingly. Owing to the suppression of the ultra-short-channel effects, excellent subthreshold swing is also successfully achieved by the nano-scale regime. Moreover, the proposed vertical structure has a path between the body and the substrate, the generated hole current by impact ionization and generated heat in channel can be banished from this pass way. Thus, both the floating-body effects and the self-heating effects are avoided synchronously

A Novel FDSOI MOSFET with Block Oxide Enclosed Body

In this paper, we propose a novel fully depleted silicon-on-insulator MOSFET with block oxide enclosed body (bFDSOI). To differ with the conventional FDSOI MOSFET, the proposed SOI structure shows enhanced performance by exploiting sidewall spacer process. For this new bFDSOI device, the electric field between the body and the source/drain (S/D) region is restrained by the block oxide resulting in that the ultra-short-channel effects (USCEs) are suppressed. Thus, the simulation results of bFDSOI exhibit reduced drain-induced barrier lowering (DIBL), excellent subthreshold swing (SS), good roll-off characteristics and high drain output resistance for 40 nm thick enough body. In order to eliminate the floating-body problem, the bFDSOI device must not be operated under the partially depleted (PD) regime. Although this is the limit of device design, as the gate length is scaled down, the requirement of the ultra-thin body (UTB) structure is not needed to maintain its ultra-short-channel characteristics control over the channel due to the block oxide serves as isolation between the body and the S/D region. Moreover, owing to that the sufficient thick body is used; the bFDSOI device results in good amelioration of self-heating effects (SHEs), which is very important in a nano-scale SOI MOSFET design

Ultra-Short-Channel Characteristics of Planar MOSFETs With Block Oxide

In this work, the investigation of block oxide used in planar MOSFETs has been studied. To solve these above issues and for the comparison, we propose two novel device architectures; one is called the FDSOI with block oxide (bFDSOI) and the other is called the Si on partial insulator with block oxide field-effect transistor (bSPIFET)

A 2D simulation study and characterization of a novel vertical SOI MOSFET with a smart source/body tie

A novel vertical silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a smart source/body contact, SSBVMOS, is presented here for the first time. 2D simulations reveal that the SSBVMOS reduces self-heating effects, with the lattice temperature reduced by 14% and the hole temperature reduced by 25%. The SSBVMOS also eliminates the floating body effect, something that other SOI vertical MOSFETs are unable to accomplish, regardless of the thickness of the thin film. The SSBVMOS is further found to have a better drain-induced barrier lowering and subthreshold swing than either a conventional vertical MOSFET or an SOI vertical MOSFET. Moreover, these results are achieved using typical pillar heights and buried oxide thicknesses. Should future technological advances allow for lower pillars or thinner buried oxides, the SSBVMOS performance would further increase.

Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI

In this work, a novel fully depleted silicon-on- insulator MOSFET with block oxide (bFDSOI) is proposed to investigate the influence of Si-body thickness on the characteristics of the device. Based on the two-dimensional (2-D) simulation results, the proposed structure exhibits better ultra-short-channel behavior such as reduced drain-induced barrier lowering (DIBL) and better subthreshold swing when compared with that of a conventional ultra-thin body (UTB) SOI structure. Furthermore, thanks to the presence of thick Si-body, the bFDSOI FET also shows reduced thermal effects that can help to improve the device reliability.

A Nanoscale bSPIFET to Overcome CMOS Scaling

In this paper, we are working on a probe into the effects of gate length (Lg) variation upon the nanoscale silicon on partial insulator field-effect transistor with block oxide (bSPIFET) being use for deca-nanometer age

An investigation of the effects of Si thickness-induced variation of the electrical characteristics in FDSOI with block oxide

This paper is submitted with an investigation concerning the effects of the Si thickness-induced variation of the electrical characteristics in the FDSOI with block oxide. We noticed that the traditional sidewall spacer process is used and processed to produce the block oxide enclosing the Si-body in our proposed structure, the undesirable ultra-short-channel effects can be significantly diminished via the suppressed charge sharing out of the source/drain to the body, as compared to the conventional UTBSOI MOSFET. Also, owing to the required thickness of the Si-body, the self-heating problem gets improved, so the reliability of these structures be upgraded and benefit a renewed interest in the single-gate FDSOI MOSFET for the future ULSI applications

A Impact of Block Oxide on 50 nm Gate Length Planar MOSFETs

In this paper, a new field-effect transistor (FET), silicon on partial insulator with block oxide (bSPI), is presented. To fabricate this novel device architecture, a sidewall spacer process is also exploited. For bSPIFET, this block oxide can block the most parts of the p-n junction between the substrate and the source/drain (S/D) region; thus, the junction leakage current is reduced dramatically. Likewise, thanks to the electric field between the body and the S/D region is isolated by the block oxide, the ultra-short-channel effects (USCEs) is also suppressed. In other words, the excellent device properties of the bSPIFET can be achieved, such as reduced drain-induced barrier lowering (DIBL), ultra low leakage (ULL), ideal subthreshold swing (SS), high drain output resistance and increase in the breakdown voltage. Moreover, owing to that the body of the bSPIFET device is bound to the substrate, both the floating-body effects (FBEs) and the self-heating effects (SHEs) are overcome simultaneously

A novel vertical sidewall MOSFET using smart source/body contact without floating-body effect

In this paper, we present a new vertical MOS device having smart source/body contact (SSBVMOS). This vertical sidewall MOSFET possesses vertical channel, sidewall gate, and body passway which allow the conduction of both the generated carriers and heat. Thus, the fabricated device can achieve low self-heating effect and good suppression of the floating body effect without occupying excessive area.