Tom Vandeweyer

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP, the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS® process is used, realizing narrow trenches with larger DOF and less LER. For mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations due to topography during the second litho step. For all these problems, solutions or work-arounds have been found, After the second MHM-etch, the 50nm half-pitch pattern is transferred successfully in the underlying low-k material.

Double patterning lithography for 32 nm: critical dimensions uniformity and overlay control considerations

Double patterning lithography (DPL)-either with two litho and two etches or through the use of a sacrificial spacer-are comparable in complexity and process control requirements. Since critical dimensions uniformity (CDU) and overlay requirements are considerably tighter than in single exposure, they present tougher challenges to process control, metrology, and integration, but seem feasible for 32-nm node. We study CDU and overlay requirements and performance at 32-nm-hp resolution for dual litho-etch and sacrificial spacer schemes. We bring in three particular aspects of CD control: the existence of multiple populations of lines and spaces, overlay entanglement into CDU performance, and the mechanism of doubled-pitch pattern generation from uncorrelated left and right edges, Accordingly, active compensation schemes are proposed to bring together these multiple CDU populations in order to achieve the typical 10% CD tolerance of the final pattern. Experimental results confirmed our assumptions of CDU-overlay entanglement and existence of multiple CD populations of lines and spaces. We present CDU results from before and after applying CD compensation schemes to improve CDU and overlay performance through active feed forward corrections. Results confirm the gain in improving statistical and spatial CD distribution to meet control levels required at 32-nm design rules: 2-nm CDU control per population, 3-nm CDU control for two adjacent lines, or spacer CD populations with 3-nm single machine overlay, all of them being demonstrated on multiple wafers and immersion scanners.

Double patterning for 32nm and below: an update

Double patterning lithography - either with two litho and etch steps or through the use of a sacrificial spacer layer, have equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to process control, metrology and integration, but seem feasible for the 32nm node. In this paper, we report results in exploring CDU and overlay performance at 32nm 1/2 pitch resolution of two double patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple populations in order to meet comparable 10% CDU as in single exposure. We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU populations entangled overlay into CDU.

Calibration and verification of a stochastic model for EUV resist

Line width roughness remains a critical issue when moving towards smaller feature sizes in EUV lithography. We present a stochastic resist modeling approach to accurately predict LWR and CD simultaneously. The stochastic model simulates the roughness effects due to the shot noise and secondary electron effects during exposure, and the interaction amongst the finite number of chemical molecules (inhibitor, PAG, quencher) during PEB. The model calibration used the imec baseline EUV resist (Shinetsu SEVR140) with over 250 measured CDs and corresponding line width roughness data. The validation was performed with 1D and 2D patterns. Especially for contact holes the predictability regarding local CD uniformity is discussed. The good match between the simulations and wafer results for SRAM patterns further exhibits the predictive power of the model. The model has been applied to simulate the new ASML NXE: 3100 EUV conditions for both thin and thick absorber EUV masks. The comparison between the simulation results and wafer data are reported.

Low temperature plasma-enhanced ALD enables cost-effective spacer defined double patterning (SDDP)

The inherent advantages of the Plasma-Enhanced Atomic Layer Deposition (PEALD) technology—excellent conformality and within wafer uniformity, no loading effect—overcome the limitations in this domain of the standard PECVD technique for spacer deposition. The low temperature process capability of PEALD silicon oxide enables direct spacer deposition on photoresist, thus suppressing the need of a patterned template hardmask to design the spacers. By decreasing the number of deposition and patterning steps, this so-called Direct Spacer Defined Double Patterning (DSDDP) integration reduces cost and complexity of the conventional SDDP approach. A successful integration is reported for 32 nm half-pitch polysilicon lines. The performances are promising, especially from the lines, which result from the PEALD spacers: Critical Dimension Uniformity (CDU) of 1.3 nm and Line Width Roughness (LWR) of 2.0 nm.

Litho and patterning challenges for memory and logic applications at the 22-nm node

In this paper we look into the litho and patterning challenges at the 22nm node. These challenges are different for memory and logic applications driven by the difference in device layout. In the case of memory, very small pitches and CDs have to be printed, close to the optical diffraction limit (k1) and resist resolution capability. For random logic applications e.g. the printing of SRAM, real pitch splitting techniques have to be applied for the first time at the 22nm node due to the aggressive dimensions of extreme small and compact area and pitch of SRAM bitcell. Common challenges are found for periphery of memory and random logic SRAM cells: here the Best Focus difference per feature type, limits the Usable Depth of Focus.

Demonstration of scaled 0.099µm 2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

We demonstrate electrically functional 0.099µm² 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L<inf>g</inf>∼40nm, 12–17nm wide Fins, and cell β ratio ∼1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ≥30nm-wide contacts. SRAM cell with SNM≫10%V<inf>DD</inf> down to 0.4V, and healthy electrical characteristics for the cell transistors [SS∼80mV/dec, DIBL∼50–80mV/V, and |V<inf>Tlin</inf>|≤0.2V (PMOS), V<inf>Tlin</inf>∼0.36V (NMOS)] are reported.

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Today, 22nm node devices are built using 193nm immersion lithography, possibly combined with double patterning techniques. Some stretch till the 16nm node is feasible here, using double, triple or even quadruple patterning. Alternatively, extreme ultra violet (EUV) lithography is showing promising results, and is considered to be the most likely option for this last mentioned device node. Electrically functional 22nm node devices are already available, where EUV lithography is used for the definition of the back-end layers. Fewer results are published on the patterning of front-end layers using EUV lithography. In this work, EUV lithography is used for the patterning development of the first four critical layers (active or fin, gate, contact and metal1) of a 16nm node 6T-SRAM cell. For the first time, front-end layers will need to be printed, with EUV, and transferred into an underlying substrate. The need for optical proximity correction is checked and characterized for all layers.

Comprehensive approach to MuGFET metrology

As we move forward to the 45 and 32nm node, MuGFETs (Multi-Gate Field-Effect Transistor) are considered more and more as a necessary alternative to keep pace with Moores Law. If proven manufacturable, MuGFETs could eventually replace conventional CMOS transistors within a few years. The ability to perform proper and extensive metrology in a production environment is then essential. We investigate here some of the requirements of MuGFET metrology. Accuracy and line width roughness (LWR) metrology will play an essential role, because the small dimension of the features involved. 3D metrology is required when dealing with non-planar devices. Sophisticated check of optical proximity correction (OPC) is needed in order to ensure that the design is respected. We propose here some possible solutions to address the needs of MuGFET metrology in a production-worthy fashion. A procedure to calibrate CDSEM to TEM for accuracy is developed. We performed LWR metrology of fins in a fully automated way by using CDSEM, while the 3D information is obtained by means of scatterometry. Finally, we will discuss the application of design-based metrology (DBM) to MuGFET OPC validation.

Dense lines created by spacer DPT scheme: process control by local dose adjustment using advanced scanner control

In this paper we present a methodology to investigate and optimize the CD balance between the four features of a final 32nm lines and space pattern created by spacer pitch doubling. Metrology (SEM and scatterometry) was optimized to measure and separate the two lines and the two spaces of the 32nm features. In case a space unbalance emerged during the various processing steps such as etch and deposition, this was compensated by calculating and feed-back local dose offsets to the scanner. For the spacer process used in this study we observe 20..40% improvement in space CDU and space balance, when applying the dose corrections.