Tomoko Ojima

Sub-100 nm pattern formation by roll-to-roll nanoimprint

Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is promising candidate for extremely low-cost fabrication of large-area devices in large volumes. We have tried to transfer sub-100 nm patterns, especially sub-30 nm patterns, onto ultraviolet (UV) curable resin on film substrate by RtR-NIL. We demonstrate a 24 nm pattern on a film substrate by RtR-NIL and the methods potential for sub-100 nm patterning.

Metrology and inspection required for next generation lithography

We summarize the metrology and inspection required for the development of nanoimprint lithography (NIL) and directed self-assembly (DSA), which are recognized as candidates for next generation lithography. For NIL, template inspection and residual layer thickness (RLT) metrology are discussed. An optical-based inspection tool for replica template inspection showed sensitivity for defects below 10 nm with sufficient throughput. Scatterometry was applied for RLT metrology. Feedback control with scatterometry improved RLT uniformity across an imprinting field. For DSA, metrology for image placement and cross-sectional profile are addressed. Design-based scanning electron microscope (SEM) metrology utilizing a die-to-database electron beam (EB) inspection tool was effective for image placement metrology. For the cross-sectional profile, a holistic approach combining scatterometry and critical dimension SEM was developed. The technologies discussed here will be important when NIL and DSA are applied for IC manufacturing, as well as in the development phases of those lithography technologies.

Patterning performance of hyper NA immersion lithography for 32nm node logic process

We have developed the lithography process for 32nm node logic devices under the 1.35NA single-exposure conditions. In low-k1 generation, we have to consider the minimum pitch resolution and two-dimensional pattern fidelity at the same time. Although strong RET (Resonance Enhancement Technique) can achieve the high image contrast, it has negative effects like line end shortening and resist pattern collapse. Moderate RET such as annular illumination can combine the minimum pitch resolution and two-dimensional pattern fidelity with hyper NA illumination condition. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 110nm for contact hole pattern, respectively. The isolated contact hole needs SRAF and focus drift exposure to improve DOF. Embedded SRAM cell of 0.125&mgr;m2 area is clearly resolved across exposure and focus window.

Challenges for pattern formation with sub-100nm residual-layer thickness by roll-to-roll nanoimprint lithography

Technologies for pattern fabrication on a flexible substrate are being developed for various flexible devices. A patterning technique for a smaller pattern of the order of sub-100 nm will be needed in the near future. Roll-to-roll Nano-Imprint Lithography (RtR-NIL) is a promising candidate for extremely low-cost fabrication of large-area devices in large volumes. A residual layer thickness (RLT) of a pattern transferred by RtR-NIL distributes at around several micrometers or more. We tried to thin the RLT below 100 nm and confirmed the controllability of the RLT and its deviation in the patterned sample.

Novel prediction methodology for etched hole patterning failure

We have created a model that uses discriminant function analysis to predict failures in etched hole patterning of the type that induces an open-contact failure by using critical dimension scanning electron microscope (CDSEM) measurement values of after-development resist hole patterning. The input variables of the best model were found to be the resist hole CD, the difference in resist hole CD between that of the 50% secondary electron (SE) threshold and that of the 20% SE threshold, and ellipticity. The model indicates that a tapered resist profile is one of the main causes of the open-contact failure in etched hole patterning. The model is applicable not only to lithography process optimization but also to lithography process control, where the focus center of optical exposure at resist patterning is determined not only from the perspective of resist CD but also from the perspective of suppressing the failures of etched hole patterning.

Resist Residue in Ion Implantation Level Lithography

We report the analysis of residual resist remaining after implantation level lithography on the topographical substrate. The problem experienced in a 45-nm-node complementary metal–oxide–semiconductor (CMOS) is described. From our experiment and simulation study, we found that switching exposure wavelength from argon fluoride (ArF) excimer lasers to krypton fluoride (KrF) excimer lasers ameliorates the issue of residual resist on gate stack substrates. In lithography over device stack such as gates, resolution cannot be explained by the Rayleigh equations k1. However, for the 32 nm node and below, ArF imaging has to be applied at ion implantation levels in view of the required resolution for a given mask layout. Therefore, we used a three-dimensional (3D) lithography simulator in order to clarify the mechanism of residual resist. From the analysis, the absorption of exposure light by sidewall materials is considered to be the reason for the residual resist. For the post-gate lithography at the ion implantation level, it is necessary to consider not only the resolution of the mask layout but the absorption of exposure light.

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.