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Dive into the research topics where Virendra R. Jadhav is active.

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Featured researches published by Virendra R. Jadhav.


electronic components and technology conference | 2009

Delamination mechanisms of thermal interface materials in organic packages during reflow and moisture soaking

Jiantao Zheng; Virendra R. Jadhav; Jamil A. Wakil; Jeffrey T. Coffin; Sushumna Iruvanti; Richard Langlois; Ed ward Yarmchuk; Michael A. Gaynes; Hsichang Liu; Kamal K. Sikka; Peter J. Brofman

A thermal interface material (TIM) is typically a compliant material with high thermal conductivity that is applied between a heat-generating chip and a heat spreader in an electronic package. For a high-conductivity polymeric TIM, the adhesion strength between the TIM and its mating interfaces is typically weak, making the TIM susceptible to degradation when subjected to environmental stresses. At typical chip operating temperatures which are below the curing temperature of the TIM, a compressive force acts on the TIM at the chip center due to the CTE mismatch between the die and the organic chip carrier. Conversely at high BGA(Ball Grid Array) or card-attach reflow temperatures, the TIM center is under tension and the TIM tends to either cohesively separate or adhesively separate from the interfaces. Also, during moisture soaking, such as 85C/85%RH, the organic chip carrier absorbs moisture and expands. The hygroscopic expansion of the organic chip carrier is of the same order of magnitude as the thermal expansion. This expansion reduces the compressive force acting on the TIM, and for certain package constructions, this can lead to degradation of thermal performance. In this paper, the delamination mechanism of a polymer-based thermal interface material in an organic package during reflow and moisture soaking is investigated. The in-situ deformation of the TIM bondline was measured by a digital image correlation (DIC) method on a cross-sectioned part. The TIM bondline deformation was also captured by a digital camera. The coefficients of thermal expansion and hygroscopic expansion for different organic materials were measured, and a finite element analysis of the hygroscopic expansion and TIM bondline deformation was conducted. The affect of T&H stress was analyzed using an equivalent CTE concept.


electronic components and technology conference | 2008

Development of a 50mm dual Flip Chip Plastic Land Grid Array package for server applications

Sylvain Ouimet; Jon A. Casey; Kenneth C. Marston; Jennifer Muncy; John S. Corbin; Virendra R. Jadhav; Thomas A. Wassick; Isabelle Dépatie

For many years, the Flip Chip Plastic Ball Grid Array (FC-PBGA) has been the preferred packaging solution for microprocessors and high performance ASICs. IBM has developed a dual chip Flip Chip Plastic Land Grid Array (FC- PLGA) package to support low and mid range server solutions. This organic 50 mm times 50 mm lead reduced package solution uses a 6-4-6 build-up laminate with two large chips consisting of a processor (22 times 16 mm) and a memory cache (15 times 13 mm) in a single piece lid capping solution. In this paper, we will summarize development activities performed in order to achieve a reliable product while dissipating up to 200 Watts mostly from the microprocessor chip. One of the many key issues to overcome was the assurance of good package thermal stability with such large silicon area coverage over the flexible organic chip carrier. Special chip and module test vehicles were designed and fabricated in order to evaluate the mechanical, electrical, and thermal behaviour of the package post assembly and throughout stress testing. The assembly process development activities performed to support the desired application will be discussed in conjunction with mechanical modeling results. In addition, thermal data will be presented showing the positive results obtained as well as good correlation to the thermal and mechanical models.


Journal of Composite Materials | 2002

Micro-mechanical modeling of polymer based unidirectional composites: Use of bulk properties of matrix with the smeared crack model

Virendra R. Jadhav; Srinivasan Sridharan

Traditional approach to micro-mechanical modeling uses in situ properties of ingredients, which are so fitted as to match predictions of the micromechanical analysis with the experimental in-plane shear response of a lamina for a particular value of fiber volume fraction. In situ properties thus derived, cannot, in general, be used with a different fiber volume fraction or a different micromechanical model. The study presented here is based on the premise that micromechanical models should be transparent and rational tools for obtaining composite properties. Therefore, an attempt is made to characterize the composite from the actual properties of the ingredients and accounting for the presence of thermal residual stresses, shear softening and micro cracking in the matrix throughout the loading history. Experimental comparisons show that a micro-mechanical model with a realistic representative volume element (RVE) and diligent accounting of matrix behavior provides good bounds on experimental response with consistent accuracy, when bulk material properties are used.


Archive | 2012

System and method of achieving mechanical and thermal stability in a multi-chip package

Jon A. Casey; John S. Corbin; David Danovitch; Isabelle Dépatie; Virendra R. Jadhav; Roger A. Liptak; Kenneth C. Marston; Jennifer Muncy; Sylvain Ouimet; Eric Salvas


electronic components and technology conference | 2005

Flip chip assembly challenges using high density, thin core carriers

Virendra R. Jadhav; Scott Preston Moore; C. Palomaki; S. Tran


Archive | 2007

Flip-chip assembly with organic chip carrier having mushroom-plated solder resist opening

Virendra R. Jadhav; Jayshree Shah; Kamalesh K. Srivastava


Archive | 2002

Stress reducing stiffener ring

David J. Alcoe; Kim J. Blackwell; Virendra R. Jadhav


Archive | 2008

Via offsetting to reduce stress under the first level interconnect (FLI) in microelectronics packaging

Virendra R. Jadhav; David L. Questad; Kamal K. Sikka; Xiaojin Wei; Jiantao Zheng


Archive | 2006

Structure for controlled collapse chip connection with a captured pad geometry

Virendra R. Jadhav; Scott Preston Moore


electronic components and technology conference | 2005

Proof is in the PTH - assuring via reliability from chip carriers to thick printed wiring boards

Kevin T. Knadle; Virendra R. Jadhav

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