Wendy H. Yeh

Generating sub-30-nm polysilicon gates using PECVD amorphous carbon as hardmask and anti-reflective coating

A PECVD deposited carbon hardmask is combined with dielectric anti-reflective coating (DARC) for the patterning of sub-90nm lines with 248nm lithography. Using this CVD dual layer stack, <1% reflectivity control is demonstrated for both 248nm and 193nm lithography. The film stack is tested with an etch integration scheme to reduce polysilicon gate critical dimension (CD). The dual layer stack can be defined with less than 100nm thick photoresist. Because of the minimal resist required to open the stack, this film stack enables an integration scheme that extends conventional photoresist trim processes up to 70% of the starting line width. In addition to conventional trim process, a resistless carbon mask trim process is investigated to further shrink the gate critical dimension. The results show that the carbon hardmask has greater than 6:1 etch selectivity to polysilicon, enabling the extension of the resist trimming technique to generate sub-30nm structures using 248nm lithography.

Wafer edge polishing process for defect reduction during immersion lithography

The objective of this study was to examine the defect reduction effect of the wafer edge polishing step on the immersion lithography process. The experimental wafers were processed through a typical front end of line device manufacturing process and half of the wafers were processed with the wafer edge polishing just prior to the immersion lithography process. The experimental wafers were then run through two immersion lithography experiments and the defect adders on these wafers were compared and analyzed. The experimental results indicated a strong effect of the edge polishing process on reducing the particle migration from the wafer edge region to the wafer surface during the immersion lithography process.

Resist Poisoning-Free Advanced PECVD-Based Anti-Reflective Coating (ARC) for 90nm Technology and Beyond

A nitrogen-free (N-free) dielectric anti-reflective coating (DARC®) was cost-effectively developed in a plasma-enhanced chemical vapor deposition (PECVD) reactor to eliminate the 193nm resist poisoning interaction caused when N 2 O is used as a precursor [1]. Although it was found that even a N-free ARC could poison sensitive 193nm resists with –OH radicals [2], which either exist inherently in the ARC or result from H 2 O absorption by the ARC surface, the current investigation has revealed that it was possible to minimize resist poisoning. Our investigation showed that compressive film stress directly correlates to H 2 O resistance. Therefore, it was possible to greatly improve the ARC resistance to H 2 O absorption by creating and maintaining a process regime that makes the ARC film dense. The dense ARC film demonstrated promising lithography performance with minimal resist poisoning as well as excellent shelf life and O 2 -ashing resistance. This paper explores the N-free DARC material, its development, lithographic integration results and implementation in a production environment to eliminate 193nm resist poisoning.