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Dive into the research topics where William Brearley is active.

Publication


Featured researches published by William Brearley.


Archive | 2000

Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization

Kamalesh K. Srivastava; Jonathan H. Griffith; Mary C. Cullinan-scholl; William Brearley; Peter C. Wade


Archive | 2000

Reactive Ion Etching chamber design for flip chip interconnections

Kamalesh K. Srivastava; Peter C. Wade; William Brearley; Jonathan H. Griffith


Archive | 1996

Ball grid array by partitioned lamination process

Roy Yu; William Brearley; Kimberley Ann Kelly; Patrick Michael O'Leary; Arthur G. Merryman; James Wood


Archive | 2007

DRY ETCHBACK OF INTERCONNECT CONTACTS

Theodorus E. Standaert; William Brearley; Stephen E. Greco; Sujatha Sankaran


Archive | 1995

Apparatus for providing solder interconnections to semiconductor and electronic packaging devices

William Brearley; Laertis Economikos; Paul F. Findeis; Kimberley A. Kelly; Bouwe W. Leenstra; Arthur G. Merryman; Eric D. Perfecto; Chandrika Prasad; James Wood; Roy Yu


Archive | 1998

Apparatus and method for use in manufacturing semiconductor devices

William Brearley; Laertis Economikos; Paul F. Findeis; Kimberley A. Kelly; Bouwe W. Leenstra; Arthur G. Merryman; Eric D. Perfecto; Chandrika Prasad; James Wood; Roy Yu


Archive | 1996

Bottom-surface-metallurgy rework process in ceramic modules

Roy Yu; James Wood; Thomas Michael Biruk; Gregory S. Boettcher; William Brearley; Kimberley Ann Kelly; Bouwe W. Leenstra; Arthur G. Merryman


Archive | 2012

Block mask decomposition for mitigating corner rounding

William Brearley; Geng Han; Lars W. Liebmann


Archive | 2006

Trocken-rückätzen von verbindungskontakten

William Brearley; Stephen E. Greco; Sujatha Sankaran; Theodorus E. Standaert


Archive | 2016

OPTICAL RULE CHECKING FOR DETECTING AT RISK STRUCTURES FOR OVERLAY ISSUES

Shayak Banerjee; William Brearley

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