Yue Ying Ong

Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package

Because of Moores (scaling/integration) law, the Cu/low-k silicon chip is getting bigger, the pin-out is getting higher, and the pitch is getting finer. Thus, the conventional organic buildup substrates cannot support these kinds of silicon chips anymore. To address these needs, Si interposer with TSV has emerged as a good solution to provide high wiring density interconnection, to minimize CTE mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress, and to improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21×21 mm Cu/low-k test chip on FCBGA package. The Cu/low-k chip is a 65 nm, 9-metal layer chip with 150 µm SnAg bump pitch of total 11,000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25×25×0.3 mm with CuNiAu as UBM on the top side, and SnAgCu bumps on the underside. The conventional BT substrate size is 45×45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free micro solder bumps and underfill have been set up. The FCBGA samples have been subjected to moisture sensitivity test and thermal cycling (TC) reliability assessments.

Electromigration study of 50 µm pitch micro solder bumps using four-point Kelvin structure

Electromigration (EM) of micro bumps of 50 µm pitch was studied using four-point Kelvin structure. Two kinds of bumps, i. e., SnAg solder bump and Cu post with SnAg solder were tested. These bumps with thick Cu under bump metallization (UBM) were bonded with electroless Ni/Au (ENIG) pads. The results showed different EM features comparing with larger flip chip joints. Under various test temperatures from 100 to 140 °C, the increasing of electrical resistance under current stressing was mainly due to the formation of the high temperature intermetallic compounds (IMCs). The resistance increase-rate in solder bump interconnects was faster than that of Cu post with SnAg bump joints since there was more low temperature solder and under current stressing, more IMCs would be formed. When Cu post with SnAg bumps were tested at 140 °C with the current density of 4.08×104 A/cm2, after certain stressing time the resistances would reach a plateau region, where the diffusion between different materials, i. e., Cu, Ni and Sn reached equilibrium, and IMCs became stable. Large number of Kirkendall voids and a number of cracks were found in the Cu post interconnects which was caused by the electron wind since less voids and cracks were found in the adjacent bump interconnects. When Cu post with SnAg bumps were tested at 140 °C with the current density of 2.04×104 A/cm2 for 1000 h, the resistance did not reach steady state. The electron flow direction also has an effect on the diffusion of materials. The degradation of resistance increased faster when electrons flow from Cu UBM to ENIG.

Development of Large Die Fine-Pitch Cu/Low-

The continuous push for smaller bump pitch interconnection in line with smaller Cu/low-k technology nodes demands the substrate technology to support finer interconnection. However, the conventional organic buildup substrate is facing a bottleneck in fine-pitch wiring due to its technology limitation, and the cost of fabricating finer pitch organic substrate is higher. To address these needs, Si interposer with through silicon via (TSV) has emerged as a good solution to provide high wiring density interconnection, and at the same time to minimize coefficient of thermal expansion mismatch to the Cu/low-k chip that is vulnerable to thermal-mechanical stress and improve electrical performance due to shorter interconnection from the chip to the substrate. This paper presents the development of TSV interposer technology for a 21 × 21 mm Cu/low-k test chip on flip chip ball grid array (FCBGA) package. The Cu/low-k chip is a 65-nm nine-metal layer chip with 150-μm SnAg bump pitch of total 11 000 I/O, with via chain and daisy chain for interconnect integrity monitoring and reliability testing. The TSV interposer size is 25 × 25 × 0.3 mm with CuNiAu as under bump metallization on the top side and SnAgCu bumps on the underside. The conventional bismaleimide triazine substrate size is 45 × 45 mm with BGA pad pitch of 1 mm and core thickness of 0.8 mm. Mechanical and thermal modeling and simulation for the FCBGA package with TSV interposer have been performed. TSV interposer fabrication processes and assembly process of the large die mounted on TSV interposer with Pb-free solder bumps and underfill have been set up. The FCBGA samples have passed moisture sensitivity test and thermal cycling reliability testing without failures in underfill delamination and daisy chain resistance measurements.

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This paper presents the assembly optimization and charcterierization of Through-Silicon Vias (TSV) interposer technology for two 8 × 10mm2 micro-bumped chips. The two micro-bumped chips represent different functional dies in a System-in-package (SiP). In the final test vehicle, one of the micro-bumped chips had 100μm bump pitch and 1,124 I/O; the other micro-bumped chip had 50μm bump pitch and 13,413 I/O. The TSV interposer size is 25 × 25 × 0.3mm3 with CuNiAu as UBM on the top side and SnAgCu bumps on the underside. The conventional substrate size is 45 × 45mm2 with 1-2-1 layer configuration, a ball-grid array (BGA) of 1mm pitch and a core thickness of 0.8mm. The final test vehicle was subjected to MSL3 and TC reliability assessment. The objective of this paper was to incorporate two 8 × 10mm2 micro-bumped chips into TSV interposer. The micro-bumped chips should have no underfill voiding issue and the whole package should be able to pass Moisture Sensitivity Level 3 (MSL3) and Thermal Cycling (TC) reliability assessment. To achieve this objective of incorporating micro-bumped chips into the TSV interposer, the challenges were small standoff height/ low bump pitch of the micro-bumped chip, underfill flowability and its reliability performance. To overcome these challenges, different types of capillary flow underfill, bump layout designs and bump types were evaluated and a quick reliability assessment was used to select the materials and test vehicle parameters for final assembly and reliability assessment.

FCBGA Package With Through Silicon via (TSV) Interposer

This paper presents a systematic underfill selection and characterization methods for 21 ×21 mm2 Cu/low-K flip chip packages (65 nm technology) with 150 μm bump pitch. This paper has also correlated the underfill characterization methods with the reliability results of 15×15 mm2 and 21×21 mm2 Cu/low-K flip chip packages. From the validations of underfill selection and characterization approach with the reliability of 21×21 mm2 Cu/low-K flip chip package, it was found that the reliability results correlated well with the adhesion test results. Underfill/flux compatibility and underfill flow performance are found to be important factors during underfill selection. Underfill should not be sieved out at the initial stage without actual reliability tests.

Assembly and reliability of micro-bumped chips with Through-silicon Vias (TSV) interposer

In this paper, a systematic underfill selection approach has been presented to characterize and identify favorable underfill encapsulants for 21 times 21 mm2 flip chip ball grid array (FCBGA) package with 150 mum interconnect pitch. A total of six evaluation factors of equal ranking weightage were considered in this underfill selection approach. Based on the approach adopted, we have selected the best underfill material suitable for 15 times 15 mm2 FCBGA packages. The target property ranges for underfill materials proposed by the IBM are further being refined. Now, a wider choice of underfill material was found to be applicable for 15 times 15 mm2 FCBGA packages. The new approach has helped to widen the selection criteria for underfill material used in 15 times 15 mm2 FCBGA packages. These findings will assist researchers in having a wider option in underfill selection for future FCBGA packages, which are more challenging.

Underfill Selection, Characterization, and Reliability Study for Fine-Pitch, Large Die Cu/Low-K Flip Chip Package

Elelctrochemical migration (ECM) test was conducted for fine pitch flip-chip micro bump interconnect. Two kinds of micro bump. i. e., Cu post with SnAg solder and Cu under bump metallization (UBM) with SnAg solder bumps in 50 and 100 µm pitch with non clean flux were used for chip interconnection. The test was conducted under 85ºC/85H condition with various biases. The results indicated that for micro bump with underfill, test with different bias and pitch showed that the smaller the pitch, the higher the bias, the easier for insulation resistance (IR) value drop. By top-down grinding, dendrites were detected and the main compositions of the dendrites were Cu and Sn. The ECM tests confirmed that even with underfill, ECM failure is a concern for micro bump interconnects with fine pitch down to 50 µm. The mechanism of the dendrite formation was proposed and it was believed that the adsorption of water steam by underfill materials and the existence of residual flux were the main reasons for the dendrites formation.

A Systematic Underfill Selection Methodology for Fine Pitch Cu/Low-k FCBGA Package

This paper focused on design, assembly and reliability assessments of 21 × 21 mm2 Cu/Low-K Flip Chip (65 nm technology) with 150 ¿m bump pitch. Metal redistribution layer (RDL) and polymer encapsulated dicing lane (PEDL) were applied to the chip wafer to reduce the shear stress on the Cu/low-K layers and also the strain on the solder bumps. The first level interconnects evaluated were Pb-free (97.5Sn2.5Ag), High-Pb (95Pb5Sn) and Cu-post/95Pb5Sn. Two different die thicknesses, such as 750 ¿m and 300 ¿m, were evaluated. the flip chip assembly of high-pb test vehicles required the right choice of flux and special alignment between the high-pb solder bumps and substrate presolder to ensure proper solder bumps and substrate pre-solder alloy wetting. Finite Element Modeling (FEM) was performed to investigate the impact of different underfill, on the inelastic strain of the outermost bumps and shear stress in the Cu/low-K layer. JEDEC standard reliability were performed on the test vehicles with different first level interconnects, die thickness, underfill materials and dicing methods.