Axel Nackaerts

AC NBTI studied in the 1 Hz -- 2 GHz range on dedicated on-chip CMOS circuits

We describe on-chip circuits specially designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer. The circuits are designed to allow measurements in multiple modes, specifically, DC and AC NBTI (both interrupted and on-the-fly), on a single pFET and on a CMOS inverter, as well as charge-pumping characterization of the stressed pFET. The results indicate that AC NBTI is independent of the frequency in the 1 Hz-2 GHz range. The voltage and stress time acceleration is observed to be identical for both AC and DC NBTI stress

Direct Measurement of Top and Sidewall Interface Trap Density in SOI FinFETs

Conventional charge pumping is demonstrated on triple-gate silicon-on-insulator FinFET gated-diode structures with varying fin widths. A simple technique is proposed and verified allowing to independently estimate fin top and sidewall interface trap density. A higher interface state density on the sidewalls is observed, which is attributed to higher fin sidewall roughness. The methodology is also demonstrated to be sensitive to fin sidewall surface crystallographic orientation. The technique presents a straightforward means of assessing the fin sidewall and topwall interface quality, which can then be directly correlated with both processing influences and reliability effects

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

First observation of FinFET specific mismatch behavior and optimization guidelines for SRAM scaling

Vt-mismatch, and thus SRAM scalability, is greatly improved in narrow SOI FinFETs, with respect to planar bulk, because of their undoped channel and near-ideal gate control. We show by simulations and by measurements that in FinFETs, unlike planar bulk, beta-mismatch becomes dominant, leading to radically different SRAM characteristics. By careful process tuning, we demonstrate a substantial reduction in beta-mismatch. We show the impact of this novel mismatch behavior on SRAM performance and yield under various optimization strategies and thereby provide guidelines for SRAM design in a FinFET technology.

Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

This work reports the first comprehensive evaluation of FUSI gates for manufacturability, covering the key aspects of integration, process control, reliability, matching, device design and circuit-level benefit. Thanks to a selective and controlled poly etch-back process, dual work-function Ni-based FUSI CMOS circuits with record ring oscillator performance (high-VT applications) have been achieved (17ps at VDD=1.1V and 20pA/mum Ioff), meeting the ITRS 45nm node requirement for low power CMOS

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Multiple gate field effect transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit

Layout options for stability tuning of SRAM cells in multi-gate-FET technologies

We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.

Impact of Cu contacts on front-end performance: a projection towards 22nm node

In this paper, we investigate the impact of replacing tungsten (W) by a Cu-based contact module. Our experiments show that a 50% reduction in contact resistance can be obtained. This is attributed to both the choice of barrier as well as filling material. An increased drive current is measured on narrow transistors with single contacts. The intrinsic gate oxide reliability is not compromised. Results on demonstrator ring oscillator structures show how the parasitic contribution to the transistor series resistance will increasingly impact circuit delay and power dissipation upon scaling. Cu is presented as a viable solution to postpone these effects by at least one node