Bikas Maiti

Growth and surface chemistry of oxynitride gate dielectric using nitric oxide

Oxynitride films grown on preoxidized (100) silicon surfaces in a nitric oxide (NO) ambient at 950 °C have been investigated using x‐ray photoelectron spectroscopy (XPS), secondary ion mass spectrometry (SIMS), atomic force microscopy (AFM), and cross‐sectional transmission electron microscopy (XTEM). Compared to N2O oxynitride, NO oxynitride exhibits very different surface chemistry, interface properties, and growth mechanisms. The etch back of NO and N2O oxynitride films allows control of sample thickness for the XPS measurements. NO oxynitride has the interfacial nitrogen (Nint) sharply peaked on the Si substrate side of the interface, while it is broad and on the dielectric side of the interface for the N2O oxynitride. The N(1s) XPS results reveal a clear distinction between N2O oxynitride and NO oxynitride. Near the Si/dielectric interface the NO oxynitride shows primarily Si≡N bonds, while the N2O films showed a N(1s) binding energy peak that is in‐between that of Si≡N bonds and Si2=N—O bonds. Furth...

Furnace grown gate oxynitride using nitric oxide (NO)

Gate oxynitride was grown in NO for the first time. This approach can provide a tight N accumulation near the Si/SiO/sub 2/ interface. Much lower thermal budget is required for an NO process than for an N/sub 2/O process to produce an oxynitride with useful properties. Submicron MOSFETs with NO oxynitride showed superior current drive characteristics and comparable hot carrier immunity to those with N/sub 2/O oxynitride. >

Growth and Film Characteristics of N 2 O and NO Oxynitride Gate and Tunnel Dielectrics

Film characteristics of thin oxynitride dielectrics grown in nitrous oxide (N 2 O) and nitric oxide (NO) gas ambients at 950°C were investigated by secondary ion mass spectrometry, x-ray photoelectron spectroscopy, atomic force microscopy (AFM), and cross-sectional transmission electron microscopy. Compared to N 2 O oxynitride, NO oxynitride exhibits very different surface chemistry, interface properties, and growth phenomena. NO oxynitride has the N int sharply peaked on the Si substrate side of the interface, while it is broad and on the dielectric side of the interface for the N 2 O oxynitride. The N (1s) XPS results reveal a clear distinction between N 2 O oxynitride and NO oxynitride. Near the Si/dielectric interface the NO oxynitride shows primarily Si?N bonds, while the N 2 O films showed a N (1s) binding energy peak that is in between that of Si?N bonds and Si 2 =N-O bonds. Further, the NO oxynitride surface roughness as determined by AFM is lower than that of the Si/SiO 2 interface. The film characteristics of N 2 O and NO oxynitrides after reoxidation in O 2 ambient are different. An anomalous increase in N int content and a decrease in oxygen content of these oxynitrides were observed as a result of reoxidation in oxygen ambient. These results are explained on the basis of changes in matrix composition of reoxidized oxynitride films.

PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

We report here for the first time an evaluation of a polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) metal gate integration on sub-quarter micron CMOSFETs using bulk Si and FDSOI substrates. In addition to eliminating poly depletion effects and lowering gate line resistance, the use of the TiN gate enables lower Vt when used with FDSOI substrates instead of bulk Si. Excellent on-off and short channel characteristics can be obtained with the TiN gate. Issues associated with Leff and reliability are also discussed.

0.18 /spl mu/m metal gate fully-depleted SOI MOSFETs for advanced CMOS applications

We report here for the first time a 0.18 /spl mu/m fully-depleted SOI process with PVD TiN metal gate. As midgap work function metal gate and very light channel doping were used, threshold voltage can be easily controlled in /spl plusmn/300 mV to /spl plusmn/500 mV range and on-wafer V/sub t/ variation was only about /spl plusmn/5 mV. Short channel effects can be further improved when silicon film thickness is thinner than 300 /spl Aring/. Subthreshold slope was kept below 75 mV/dec even for subnominal devices and V/sub t/ roll-offs for both N- and P-MOSFETs were very small.

Gate oxynitride grown in nitric oxide (NO)

Gate oxynitride was grown in NO for the first time. This approach can provide a tight N accumulation near the Si/SiO/sub 2/ interface. Much lower thermal budget is required for an NO process than an N/sub 2/O process to produce an oxynitride with useful properties. Submicron MOSFETs with NO oxynitride showed superior current drive characteristics and comparable hot carrier immunity to those with N/sub 2/O oxynitride.<<ETX>>

Sub-quarter micron CMOS process for TiN-gate MOSFETs with TiO/sub 2/ gate dielectric formed by titanium oxidation

We report here for the first time the integration of sub-quarter micron CMOSFETs on bulk silicon using an oxidized metal gate dielectric. A polysilicon capped physical vapor deposited (PVD) titanium nitride (TiN) was used as the gate electrode. Well behaved MOSFET characteristics were obtained. In this paper, we present results on the physical and electrical characterization of titanium dioxide (TiO/sub 2/) produced by oxidizing a thin PVD Ti film.

Metal gates for advanced CMOS technology

This paper will provide an overview of the emerging trends in metal gate solutions for advanced CMOS technology. Performance enhancement in silicon-based CMOS technology through MOSFET scaling has shown some limitations with the current polysilicon gate electrode. Replacing polysilicon gate electrode by metal appears to be promising. However, the choice of the metal gate material depends on its work functions, thermal/chemical stability with surrounding materials, process integration, deposition process, resistivity, and eventually performance, reliability and future scaling. This paper will discuss some of the result published in the literature that address some of these issues and propose future directions. Single mid-gap metal gate approach appears to be simpler from an integration point of view but achieving low MOSFET threshold voltage is a concern. Some channel engineering approaches have been reported to address this issue. Dual metal gate approach with work function similar to n+ and p+ doped poly-Si appears ideal, although processing complexity could be a hindrance. Also the need for inlaid gate integration could be enhanced because of thermal/chemical stability effects of metal gate electrode with underlying gate dielectric, the inability to etch new materials or to reduce device instability due to film stress as in the conventional approach. The performance improvement of CMOS devices has been estimated with metal gates along with reliability issues.

High performance 20 /spl Aring/ NO oxynitride for gate dielectric in deep subquarter micron CMOS technology

In this paper we report excellent performance of 20 /spl Aring/, gate oxide annealed in nitric oxide (NO oxynitride) as gate dielectric in sub-quarter micron CMOSFETs. We show that the degradation of current drive and peak transconductance in MOSFETs, previously observed in oxynitrides, can be eliminated by threshold voltage (Vt). Robust reliability characteristics are described for 20 A NO oxynitride.

Novel process for reliable ultrathin tunnel dielectrics

A new process technique, referred to as the ‘‘oxidized‐nitrided silicon (ONS),’’ was developed for producing ultrathin (≤50 A) dielectrics. Metal‐oxide‐semiconductor capacitors were fabricated using this novel process to investigate the dielectric quality. It was found that devices with ONS dielectrics exhibit reduced charge trapping and improved interface‐state generation characteristics. The stress‐induced leakage current, which is one of the major concerns for ultrathin dielectrics, was also suppressed by employing the ONS dielectrics. In addition, precise thickness control can be easily achieved by the ONS process even down to the ultrathin regime. The results suggest that this novel ONS process can synthesize reliable tunnel dielectrics suitable for memory applications.