Christina Baerts

High yield sub-0.1µm 2 6T-SRAM cells, featuring high-k/metal-gate finfet devices, double gate patterning, a novel fin etch strategy, full-field EUV lithography and optimized junction design & layout

We report high yield sub-0.1µm2 SRAM cells using high-k/metal gate finfet devices. Key features are (1) novel fin patterning strategy, (2) double gate patterning (3) new SRAM cell layout and (4) EUV lithography and robust etch/fill/CMP for contact/metal1. 0.099µm2 finfet 6T-SRAM cells show good yield. And smaller cells (0.089µm2) are functional. Further yield improvement is possible by junction optimization using extension less junction approach and further cell layout optimization.

Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

RMG nMOS 1 st process enabling 10x lower gate resistivity in N7 bulk FinFETs

A novel RMG process in which the n-type work function metal (nWFM) is deposited first and then selectively removed from the pMOS devices is presented for the first time. The key benefit of this nMOS 1st process lies in increased gate-fill space which results in about 10× improvement in the pMOS effective gate resistivity at gate lengths (LG) around 22 nm, an improvement which is predicted by modeling to extend down to LG<;14 nm. The complete removal of the nWFM in the pMOS devices is evidenced by restored p-type effective work function (eWF) values in large area capacitors and matched pMOS threshold voltage (VT) values in bulk FinFET devices with LG down to 22 nm. Furthermore, selective removal of the nWFM is confirmed physically down to LG~16 nm providing further evidence that the process is scalable towards N7 dimensions.

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274/spl mu/m2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.