Erik Bury

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

High-Mobility n-MOSFET options with Ge and InGaAs channels are of intense interests. As the well-known interfacial trap (Dit) problem appears now contained, new challenges are emerging from above the interface. The evidence of oxide border traps (BT) in high-k dielectrics and its effect on the on-state performance of Ge and InGaAs n-MOSFETs are presented in this study through combined trap and transport analyses. The impact of the oxide traps on device frequency response and threshold voltage (Vth) stability could challenge the commercial realization of the high mobility channel MOSFET.

Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology

Here we show that nFET and pFET time-dependent variability, in addition to the standard time-zero variability, can be fully characterized and projected using a series of measurements on a large test element group (TEG) fabricated in an advanced High-k/Metal Gate (HK/MG) technology, thus allowing us to fully characterize the underlying technology. BTI is shown to follow a bimodal defect-centric behavior, for NBTI related to Interface Layer (IL)(SiO2) and HK trapping and for PBTI related to HK and IL/HK interface trapping. Moreover for the first time, an analytical description of the bimodal total ΔVTH shift is derived, as a special case of the generalized defect-centric distribution, which we derive in this work to accurately describe the tail of the distribution.

Origins and implications of increased channel hot carrier variability in nFinFETs

Channel hot carrier (CHC) stress is observed to result in higher variability of degradation in deeply-scaled nFinFETs than bias temperature instability (BTI) stress. Potential sources of this increased variation are discussed and the intrinsic time-dependent variability component is extracted using a novel methodology based on matched pairs. It is concluded that in deeply-scaled devices, CHC-induced time-dependent distributions will be bimodal, pertaining to bulk charging and to interface defect generation, respectively. The latter, high-impact mode will control circuit failure fractions at high percentiles.

Self-heating on bulk FinFET from 14nm down to 7nm node

Self-heating effects in scaled bulk FinFETs from 14nm to 7nm node are discussed based on 3D FEM simulations and experimental measurements. Following a typical 0.7x scaling, heat confinement is expected to increase by 20% in Si-channel FinFETs and by another 57% for strained Ge-channel. Reducing the drive current needed to reach target performance by reducing capacitances, and fin depopulation help mitigate self-heating effects. These thermal behaviors propagates to AC circuit benchmark, resulting in ~5% performance variation for high performance devices due to device scaling and increased number of fins.

NBTI in Replacement Metal Gate SiGe core FinFETs: Impact of Ge concentration, fin width, fin rotation and interface passivation by high pressure anneals

We report a broad study of Negative Bias Temperature Instability (NBTI) in Replacement Metal Gate (RMG) SiGe core FinFETs, focusing on the impact of Ge concentration, fin width, fin side-wall orientation, and interface passivation by high pressure anneals (HPA). We focus on Si-cap-free gate stacks, which offer simplified FinFET integration. Direct oxidation of SiGe yields poor interface quality, which can be restored by HPA. Despite a wide distribution of defect levels in the interfacial layer due to Ge suboxide formation, SiGe reliability still benefits from a reduced bulk oxide trapping thanks to favorable energy decoupling of channel carriers to dielectric defect levels. Reduced NBTI is observed in narrow fins, thanks to a reduced oxide electric field. Fin rotation does not improve NBTI in SiGe fins, while some improvement, particularly of the near-interface degradation, was obtained by HPA. Our results show that Si-cap-free RMG SiGe gate stacks with properly optimized HPA can offer a simplified FinFET integration, with a limited reliability penalty compared to best-in-class Si-passivated SiGe devices.

Characterization of self-heating in high-mobility Ge FinFET pMOS devices

Based on physically-extended methodology, measurements and simulations show that implementing high-mobility materials and particularly alloys, such as a SiGe buffer for mobility enhancement in a Ge channel, can result in a 115% increase in self heating in the N7 node, compared to standard Si FinFETs.

The defect-centric perspective of device and circuit reliability — From individual defects to circuits

As-fabricated (time-zero) variability and mean device aging are nowadays routinely considered in circuit simulations and design. Time-dependent variability (reliability variability) is an emerging trend that needs to be considered in circuit design as well. This phenomenon in deeply scaled devices can be best understood within the so-called defect-centric picture in terms of an ensemble of individual defects and their time, voltage, and temperature dependent properties. The properties of gate oxide defects are discussed and it is shown how these properties can be used to construct time-dependent variability distributions and can be propagated up to transistor-level circuits.

Self-heating in FinFET and GAA-NW using Si, Ge and III/V channels

The self-heating (SH) effect is studied experimentally and through simulations on an extensive set of industry-relevant solutions for FF and GAA-NW Si and high-mobility devices, with multiple processing options. Considerations for managing SH in future technologies are provided.

NBTI in Si 0.55 Ge 0.45 cladding p-FinFETs: Porting the superior reliability from planar to 3D architectures

SiGe channel planar pMOSFETs have been recently shown to offer improved NBTI reliability, owing to reduced hole trapping into pre-existing oxide defects and reduced interface state generation. In this paper we report a broad set of experimental data of SiGe cladding finFETs with varying fin widths, and we show that the intrinsically superior NBTI reliability can be ported to 3D architectures of relevance for N10 and beyond. The underlying physical mechanisms are discussed and compared to planar technologies.

Uncovering the temperature of the hotspot in nanoscale devices

We present for the first time multi-scale modeling of self-heating effects in conventional MOSFET devices in a common-source and common-drain configurations in which one of the devices is the device under test (DUT) and the other device is the sensor. Via comparisons to experimental measurements performed at IMEC, we are able to uncover the temperature of the hot spot. This is also the first study in which a circuit with two transistors is being simulated using thermal particle-based device simulations.