Cheng-Kuo Wen

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

High performance dual-gate ISFET with non-ideal effect reduction schemes in a SOI-CMOS bioelectrical SoC

A dual-gate ion-sensitive field-effect transistor (DGFET) with the back-side sensing structure implemented in a 0.18 μm SOI-CMOS SoC platform realizing high performance bioelectrical detection with non-ideal effect reduction is presented. Non-ideal effects of the conventional ISFET, such as time drift and hysteresis, are suppressed by the innovative scheme in DGFET using the bottom poly-gate (PG) transistor instead of the fluidic gate (FG) transistor for sensing. As a result, the signal-to-noise ratio (SNR) is improved by 155x, time drift is reduced by 53x, and hysteresis is reduced by 3.7x. For certain applications which require high sensitivity, a pulse-modulated biasing technique can be adopted to effectively reduce time drift with high pH sensitivity of 453 mV/pH which is ~7.5x enhancement over the Nernst limit in the proposed DGFET.

45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell

The first 45nm node planar-SOI technology has been developed with 6T-SRAM cell of 0.296 /spl mu/m/sup 2/. An adequate static noise margin of 120mV is obtained even at 0.6V operation. Fine patterning with line pitch of 130nm and contact pitch of 140nm by optical lithography is demonstrated. Transistors with 30nm gate length and 27nm slim spacer operate at 1V/0.85V with excellent drive currents of 1000/740 and 530/420 /spl mu/A//spl mu/m for N-FET and P-FET, respectively. The P-FET current is the best reported so far.

A semiconductor bio-electrical platform with addressable thermal control circuits for accelerated bioassay development

A 0.18μm SOI-CMOS bioelectrical sensing technology is introduced. An SOC chip integrates biosensor pixel arrays, controllers and amplifiers is used to demonstrate the performance of this technology. The pixel size in the pixel arrays is 10μm × 10μm, including biosensor, temperature sensor and heaters. The chip demonstrates detections of hydrogen ion concentration, enzymatic reactions and DNA hybridization with PCR. Experimental results show close to Nernst limit of 59mV/pH in ion concentration detection, sub-millimolar resolutions with 99.9% linearity in urea, and 400mV surface potential change in DNA hybridization. The SOC chip has an addressable temperature control for each pixel with embedded thermal sensors. A thermal time constant of 35msec/K and sub-degree localized temperature control are achieved. Order of magnitude improvements over previously reported are seen in both detectable minimum sample liquid volume and thermal time constant for PCR. This is a good demonstration of semiconductor technology for multi-biomarkers detection for medical applications.

Modeling isolation-induced mechanical stress effect on SOI MOS devices

In this paper, the mechanical stress effect of SOI MOS devices was analysed. The width dependence of stress effect and drain current shift were evaluated.

Strain Efficiency Enhancement with Stress Intermedium Engineering (SIE) for Sub-65nm CMOS Scaling

Abstract Performance gain arising from 40nm/0.7GPa tensile contact-etch-stop layer has been significantly amplified from intrinsic 6% up to 15% by newly developed Stress Intermedium Engineering (SIE) technology. A stress transfer model considering mechanical properties of intermedium materials is proposed to account for the performance boost. Neither worse short-channel effects nor abnormal junction leakage were found with the SIE technology. Excellent gate oxide integrity and hot carrier immunity of the SIE technology  have also been verified for manufacture implementation. This study features a new paradigm of channel strain engineering for sub-65nm CMOS scaling, in addition to conventional approach of stressor optimization. Introduction Using contact-etch-stop layer (CESL) as a stressor to strain silicon channel for higher drive current is at present the simplest and the most widely adopted strained-Si technology [1-2]. Theoretically, the induced channel strain will be increased with increasing the CESL stressor intensity and/or thickness [3-6]. However, the stressor thickness is usually limited by design rule, and even has to be reduced with device feature size scaling down. The stressor intensity is also limited by process available, from manufacture viewpoint. Under these boundary conditions, the efficiency of stress intermedium (between aforementioned stressor and the target strained channel, shown in Fig. 1) is then worth our while to explore, for fully utilizing the adopted stressor strength. So far, to the extent of our knowledge, there are no published literatures for such “stress intermedium” discussion. In this paper, our experiments including source/drain silicide engineering and junction profile modification for the stress intermedium optimization show that the CESL-stressor induced performance gain can be significantly amplified. Mechanical properties of the stress intermedium will be discussed for the first time. Device Fabrication A 65nm-gate N-MOSFET with 40nm/0.7GPa tensile CESL stressor was fabricated for the stress intermedium study. Gate spacer width and CESL stressor thickness is fixed in this work. Source/drain with Co silicide and Ni silicide are splitted for comparison. The silicide’s and neighbor junction’s profiles are optimized for minimum parasitic source/drain resistance while maintaining short-channel-effect control (i.e. the same subthreshold and junction leakage), and also for achieving maximum channel strain as so-called “stress intermedium engineering (SIE)”. Results and Discussions Amplified Performance Enhancement with SIE. Table 1 summarizes performance improvement percentages of various technologies: CESL stressor only, SIE only, and CESL stressor + SIE, over control devices. In both cases of Co silicide and Ni silicide, performance enhancement of “CESL stressor + SIE” is obviously larger than the sum of individual “CESL stressor only” and “SIE only”. Fig. 2-4 show the detailed experimental data of each performance enhancement technology with Co silicide, and Fig. 5 shows that with Ni silicide. For Id,sat comparison, minor enhancement by SIE (2% for Co silicide case and 1.5% for Ni silicide case) significantly increases performance gain of CESL stressor (from 6% up to 15%, and from 4% up to 8%, for Co and Ni silicide, respectively). The SIE also increases Id,lin, but not as much as for Id,sat, from 11% up to 16%, and from 7% up to 9%, for Co and Ni silicide, respectively. The SIE itself in our experiments is originally designed for parasitic resistance (Rext) reduction [7-8], which accounts for most of the Id,lin difference between “CESL stressor” and “CESL stressor + SIE”, but not able to make up the much bigger Id,sat difference between them. A model concerning mechanical property of intermedium materials to account for different stress transfer efficiency is therefore proposed, as schematically illustrated in Fig. 7. Stress Transfer Efficiency. Table 2 and Fig. 7 show the mechanical property of intermedium materials and the schematic of stress transfer through stress intermedium, respectively. A channel stress (σxx and σzz) simulation is used to evaluate the stress transfer efficiency at different mechanical property of intermedium (Co silicide, Ni silicide, and Si), as shown in Fig. 8. An ideal stress intermedium should be able to generate higher tensile stress on channel direction (σxx) and higher compressive stress on vertical direction (σzz) for enhancing N-MOSFET drive current [9]. This is consistent with that SIE using Co silicide shows much higher performance gain than Ni silicide under the same CESL stressor (40nm/0.7GPa), due to Co silicide with lower Young’s modulus gives rise to much higher compressive σzz at slightly degraded σxx. The more desired channel stress through engineered Co silicide and proper junction profile is herein expressed as arising from higher stress transfer efficiency with better stress intermedium. SIE Device Characteristics. The Vt roll-off characteristic of N-MOSFET with SIE and tensile CESL stressor is similar to control devices (Fig. 9). The Vt shift (~15mV) is due to band split by tensile strain. The ID-VG characteristic of a 65nm channel N-MOSFET device with SIE is shown in Fig.10. It is noticed that the subthreshold swing (100mV/dec) and leakage current (subthreshold leakage and GIDL) of the SIE assisted device are compatible to the control devices, indicating no side effects on the leakage current with optimized silicide and junction profile. The ID-VD output characteristics of the N-MOSFET device with SIE and tensile CESL stressor is shown in Fig. 11. Inversion thicknesses examination of gate oxide shows no difference between control, with SIE, and with tensile CESL + SIE (Fig. 12). Furthermore, the gate oxide integrity is not adversely affected with the SIE approach (Fig. 13). Finally, reliability test of hot carrier immunity (HCI) is also checked. Both SIE assisted and unstrained control show similar HCI lifetime (Fig. 14). Conclusions A novel Stress Intermedium Engineering technology has been developed to amplify CESL-stressor induced performance gain from 6% up to 15%. Excellent gate oxide integrity, hot carrier immunity, and also the same short-channel-effect control are achieved with this new technology. The technology enhances channel strain through stress intermedium optimization rather than increasing stressor intensity/thickness, thus is very promising for sub-65nm CMOS scaling. References [1] A. Shimizu et al., IEDM Tech. Dig., p.433-436, 2001. [2] H.S. Yang et al., IEDM Tech. Dig., p.1075-1077, 2004. [3] F.-L. Yang et al., IEDM Tech. Dig., p.627-630, 2003. [4] K. Mistry et al., Symp. on VLSI Technology, p.50-51, 2004. [5] S. Pidin et al., IEDM Tech. Dig., p.213-216, 2004. [6] S. Zhao et al., Symp. on VLSI Technology, p.14-15, 2004. [7] H. Kawasaki et al., IEDM Tech. Dig., p.169-172, 2004. [8] F. Andrieu et al., Symp. on VLSI Technology, p176-177, 2005. [9] C.H. Ge et al., IEDM Tech. Dig., p.73-76, 2003. Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006,