Geraldine Jamieson

CMOS-integrated poly-SiGe cantilevers with read/write system for probe storage device

A poly-SiGe technology enabling a dense array of micro-cantilevers and tips on CMOS is demonstrated. Built from a dual-thickness structural layer, the cantilevers feature a very small initial bending and have a compliant torsional suspension with a stiffness of 3×10−10 Nm/rad. Sharp tips are formed in a low-temperature amorphous silicon layer by isotropic plasma etching. An electrical read/write system is formed by connecting the tip to the CMOS with a suspended platinum trace, running on top of the cantilever.

Ruthenium interconnects with 58 nm 2 cross-section area using a metal-spacer process

Platinum-group metals have emerged as promising alternatives to replace Cu in scaled interconnects. Here, we present a short-loop test vehicle to fabricate metal nanowires with sub-100 nm2 cross-section area without the need for multiple patterning or CMP. Ru nanowires with 58 nm2 cross-section area, as determined by the TCR method, were realized and characterized by transmission electron microscopy and electrical measurements. The nanowires demonstrate low resistivity (27 µΩcm) and very high current carrying capacity with fusing currents as high as 720 MA/cm2.

3D integration challenges for fine pitch back side micro-bumping on ZoneBOND™ wafers

The fabrication of small pitch micro-bumps on thinned wafers after through silicon vias (TSV) reveal and back side passivation is reported. Device wafers are bonded on temporary silicon carrier using the novel ZoneBONDTM material. Micro-bump scaling involves a reduction of the overall solder volume. These structures are now reaching such dimensions that solder diffusion becomes problematic. One key advantage of the ZoneBONDTM material is to enable room temperature debonding process in case of solder bumps and therefore prevent any metal diffusion or solder consumption prior to stacking. The glue compatibility with the micro-bumping module and the challenges to perform these processes on the back side of device wafers are reported in this study. The main process steps studied are the lithography and its alignment accuracy as well as the electro chemical deposition of the micro-bumps.

Alternative patterning techniques enabling fine pitch interconnection on topography surfaces

We report on the fabrication of small pitch (20 µm) interconnection structures based on Cu pillars embedded in polymer. Such structures are useful in different applications such as integrated passives and die embedding technologies. To allow the fabrication of such structures, we made use of the diamond bit cutting and dry etching techniques as alternatives to the currently used lithographic process. This latter did not allow targeting such aggressive pitches and structures dimensions.

Process related challenges for 3D face to face stacking test vehicles using a 40/50μm pitch CuSn microbump configuration

There are several motivations for moving to 3D IC technology. One of the key factors is performance enhancement which can be achieved by further miniaturization of the IC. As more and more functionality is required on a smaller footprint, 3D stacking is a very valuable solution. The increased use of multi-chip integration schemes that use microbumps, Cu pillars and TSVs introduces however severe requirements in term of bump uniformity, height, profile and pitch making 3D stacking exponentially challenging. In this paper we introduce some of the challenges to enable microbumps with pitch of 50μm and below. We also propose process optimizations to enable 3D face to face stacking of a test vehicle. An improvement of the bump plating has been demonstrated by adding a plasma treatment prior to plating. The optimized bumping process has been validated by shear test and electrical characterization of 3D stacks.