Juan Andres Torres

RET-compliant cell generation for sub-130-nm processes

The use of Resolution Enhancement Technologies (RET) is becoming mainstream for sub-wavelength lithography processes. Optical tools will not likely meet the process requirements for sub-130nm designs on their own. Different RET are being explored and in some cases, heavily used in order to improve the process window of sub-wavelength imaging. Model-based OPC, sub-resolution assist feature and phase shift masks are some of the most common RET Methods used to achieve production-worthy imaging. Every RET has its own limitations and advantages for every specific one. Some designs will not be able to be subjected to a specific RET because the layout is not friendly to it. Manual redesign of such layouts becomes intractable for very complex design with multiple cell attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance attractive from the process integration point of view. By analysis standard cell libraries from an RET compliance perspective, it is possible to envision a methodology that can find the most RET-friendly design while maintaining the functional specification of every cell. This investigation focuses on sub-resolution assist features, alternating phase shift masks and double dipole. For most common RET approaches, minimum spacing, placement, width and feature geometry can be extracted from the RET compliance analysis. Later, a set of enhanced design rules that incorporate RET specific constraints is used to re-derive the optimal feature arrangement within the cells, until the cell meets the level of RET compliance defined by the user. Eventually, the process can be extended to ful layout compliance when all the interactions between individual cells is accounted for, and modified accordingly. The advantage of having RET compliant cell sis that during lace and route, the use can concentrate on optimizing global placement parameters instead of focusing on each individual cell. The final results will depend on the user requirements and acceptable parameters of ear, power, manufacturability, etc. This a general flow that is able to generate cells that meet electrical and manufacturing specifications and it is flexible enough to accommodate every existing RET.

Incorporating DSA in multipatterning semiconductor manufacturing technologies

Multi-patterning (MP) is the process of record for many sub-10nm process technologies. The drive to higher densities has required the use of double and triple patterning for several layers; but this increases the cost of the new processes especially for low volume products in which the mask set is a large percentage of the total cost. For that reason there has been a strong incentive to develop technologies like Directed Self Assembly (DSA), EUV or E-beam direct write to reduce the total number of masks needed in a new technology node. Because of the nature of the technology, DSA cylinder graphoepitaxy only allows single-size holes in a single patterning approach. However, by integrating DSA and MP into a hybrid DSA-MP process, it is possible to come up with decomposition approaches that increase the design flexibility, allowing different size holes or bar structures by independently changing the process for every patterning step. A simple approach to integrate multi-patterning with DSA is to perform DSA grouping and MP decomposition in sequence whether it is: grouping-then-decomposition or decomposition-then-grouping; and each of the two sequences has its pros and cons. However, this paper describes why these intuitive approaches do not produce results of acceptable quality from the point of view of design compliance and we highlight the need for custom DSA-aware MP algorithms.

Design verification flow for model-assisted double-dipole decomposition

Double-exposure techniques are currently being explored as alternatives to the low k1 problem that arises form the current absence of next-generation lithography (NGL) tools. Off-axis illumination conditions such as annular, used in conjunction with binary chrome masks are able to resolve features as small as 100nm. However, these off-axis approaches only improve a limited set of pitches. While certain features on the layout are enhanced, others loose contrast and cannot be imaged properly. Dipole illumination is the extreme off-axis case, but this high/low contrast problem is lessened by a double exposure approach. Double exposure corrections require a global optimization of tow masks. As is the case with any multi-dimensional problem, current model OPC algorithms are able to locally optimize the solution, but it is difficult to guarantee a global optimal set. Including in the correction mask-manufacturing constraints can reduce this apparent problem. By limiting the number of local optimal states accessible to the convergence criterion, it is possible to arrive at a better solution. This solution is lithographically correct and easier to manufacture. In this work we preset a data flow using models created previously for a model-assisted dipole decomposition to rank different approaches based on final image contrast, pattern fidelity and focus dependency. We also provide insights on how angled features can be successfully imaged under a double dipole approach, showing how such features need to be studied form an image formation point of view, not under simple geometric principles that rule out the presence of angled features.

3D IC TSV‐Based Technology: Stress Assessment For Chip Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D through‐silicon‐via (TSV) based technologies are outlined. A set of physics‐based compact models of a multi‐scale simulation flow for assessment of the mechanical stress across the device layers in the silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured transistor electrical characteristics of a custom designed test‐chip is proposed.

Litho aware method for circuit timing/power analysis through process

Device extraction and the quality of device extraction is becoming of increasing concern for integrated circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of 65nm and below approximation of extracting the device geometry drawn in the design layout polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore contours from lithographic simulations need to be considered for more accurate results. Process window variations have a considerable effect on the shape of the device wafer contour, having an accurate method to extract device parameters from wafer contours would still need to know which lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the best lithography conditions just enough? Is there a need to consider also process variations? How do we include them in the extraction algorithm? In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.

Directed self-assembly compliant flow with immersion lithography: from material to design and patterning

Abstract. We present a directed self-assembly (DSA) compliant flow for contact/via layers with immersion lithography assuming the graphoepitaxy process for the cylinders’ formation. We demonstrate that the DSA technology enablement needs co-optimization among material, design, and lithography. We show that the number of DSA grouping constructs is countable for the gridded-design architecture. We use template error enhancement factor to choose DSA material, determine grouping design rules, and select the optimum guiding patterns. Our post-pxOPC imaging data show that it is promising to achieve two-mask solution with DSA for the contact/via layer using 193i at 5 nm node.

Model-assisted placement of subresolution assist features: experimental results

Lithography models calibrated from experimental data have been used to determine the optimum insertion strategy of sub-resolution assist features in a 130 nm process. This work presents results for 3 different illumination types: Standard, QUASAR, and Annular. The calibrated models are used to classify every edge in the design based on its optical properties (in this case image-log-slope). This classification is used to determine the likelihood of an edge to print on target with the maximum image-log-slope. In other words, the method classifies design edges not in geometrically equivalent classes, but according to equivalent optical responses. After all the edges are classified, a rule table is generated for every process. This table describes the width and separation of the assist features based on a global cost function for each illumination type. The tables are later used to insert the assist features of various widths and separations using pre-defined priority strategies. After the bars have been inserted, OPC is applied to the main structures in the presence of the newly added assist features. Critical areas are tagged for increased fragmentation allowing certain areas to receive the maximum amount of correction and compensate for any proximity effects due to the sub-resolution assist features. The model-assisted solution is compared against a traditional rule-based solution, which was also derived experimentally. Both scenarios have model based OPC correction applied using simulation and experimental data. By comparing both cases it is possible to assess the advantages and disadvantages of both methods.

Directed self-assembly (DSA) grapho-epitaxy template generation with immersion lithography

In this paper, we present an optimization methodology for the template designs of sub-resolution contacts using directed self-assembly (DSA) with grapho-epitaxy and immersion lithography. We demonstrate the flow using a 60nm-pitch contact design in doublet with Monte Carlo simulations for DSA. We introduce the notion of Template Error Enhancement Factor (TEEF) to gauge the sensitivity of DSA printing infidelity to template printing infidelity, and evaluate optimized template designs with TEEF metrics. Our data shows that SMO is critical to achieve sub-80nm non- L0 pitches for DSA patterns using 193i.

Contrast analysis and optimization for resolution enhancement technique

We propose a framework for the analysis and characterization of the efficacy of any resolution enhancement technique (RET) in lithography. The method is based on extracting a distribution of the image log slope (ILS) for a given layout under a predefined set of optical conditions. This distribution is then taken as the optical signature for the image local contrast of the design. The optical signature can be created for an entire layout, or only for certain cells believed to be problematic. Comparisons can be made between the optical signatures generated using different illumination/RET strategies. We have used this method to evaluate and optimize two different RET approaches: subresolution assist features (SRAF) and double-exposure dipole illumination.

Directed self assembly on resist-limited guiding patterns for hole grapho-epitaxy: Can DSA help lower EUV's source power requirements?

We have performed a systematic study regarding the diblock composition to keep the size of the cylinders relatively constant despite the shape of the guiding pattern. We have also explored how some guiding patterns shapes provide acceptable cylindrical assembly using an EUV exposure system. This study assumes that LER is a random phenomenon which conformably follows the shape of the guiding pattern. While the edges of the guiding pattern have fluctuations related to the LER of the EUV resist, as long as the centroid of the guiding pattern remains constant, the rectification characteristics of DSA permits adequate hole formation. In this paper we include the level of LER a guiding pattern can exhibit given a pre-determined diblock copolymer / homopolymer mixture. As the amount of homopolymer increases, the size and placement of the assembled diblock becomes less sensitive to the guiding pattern’s edge roughness. This study also explores how the addition of homopolymer is only effective up to a point, as a homopolymer-rich blend is not able to assemble properly. One of the concerns about homopolymer-rich mixtures is the effect it has in the formation of defects. Such effect has not been fully characterized but this study serves as the basis for testing optimal combinations of materials and lithography settings for an EUV system, with the end goal to enable contact/via printing at lower EUV source power requirements.