Karl Wimmer

Monte Carlo method for highly efficient and accurate statistical lithography simulations

Recent years have shown a strong increase in the use of statistical lithography error analysis for process tuning and in making technology choices. Simulation has shown it can play an important role in this area by accurately predicting experimental critical dimension (CD) distributions. Earlier statistical lithography simulation work was based on the Response Surface Methodology. The response surface is built by simulating CD dependence on input lithography process variables of interest such as focus, dose, mask CD, resist thickness, etc. The process parameters are then sampled from the Gaussian distribution to generate the distribution of the resulting resist CDs. When a large number of input parameters are being considered in order to describe the important experimental variations, the computational runtime is rapidly increased due to the requirements to fully simulate an (N+1)-dimensional response surface, where N is the number of input parameters. The work we present here has improved the speed of statistical lithography simulations through the use of Monte Carlo technique. With this technique, the runtime of the simulations is independent of the number of input parameters. The technique can be used for 1D or 2D simulations. We present results benchmarked with 130 nm process data showing the usefulness, runtime improvements and accuracy of this method. We have also used Variable Threshold Resist model (VTRM) in conjunction with the Monte Carlo technique. VTRM was calibrated against experimental focus-exposure matrices at varying line width and pitch. The use of VTRM greatly improves the accuracy of the statistical results by the virtue of establishing a good fit to the experimental data, which can be quantified by the root mean squares of residuals. VTRM also significantly speeds up the computation, since it uses only aerial image calculation as opposed to full resist modeling. Simulation results produced by using VTRM closely match the experimental results through a range of pitches, mask line widths and various illumination conditions.

Re-evaluating simple lambda-based design rules for low-K1 lithography process control

Due to the continuing decrease of the Rayleigh lithographic K1 factor used in advanced semiconductor technology, the non- linearity between designed and printed circuit images continues to increase. This increasing non-linearity has significant implications for the layout design rules with advanced technology. Recently, industry pundits have speculated that lithographic K1 factors can go far below current value. This paper aims to understand the impact of low K1 lithography upon a set of basic, company independent, layout design rules, the lambda based rules proposed by Mead and Conway. The results show that even with the use of aggressive optical proximity correction (OPC) techniques, significant changes in layout design rules will have to be made in order to extend lithographic capability to the low K1 regime.

Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies

The impact of photoresist taper and implant tilt angle on the interwell isolation of a sub-0.25 micrometer CMOS technology is investigated. It is shown that as the trench depth is decreased and the n-well dose and energy is increased, interwell isolation below 1 micron N+/P+ spacing is degraded. The reduction of photoresist taper is shown to be a key factor in improving interwell isolation and decreasing MOSFET device parasitics. By optimizing the photoresist process to minimize taper, acceptable N+/P+ isolation is achieved down to 0.7 micrometers. Also, by utilizing a two dimensional interwell isolation test structure, it is found for the first time that as the interwell isolation is scaled into the sub-micron regime, lateral n-well dopant displacement caused by the implant tilt angle can result in reduced overlay margin.

Combining OPC and design for printability into 65-nm logic designs

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.

Process, design and optical proximity correction requirements for the 65nm device generation

The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.

Impact of optimized illumination upon simple lambda-based design rules for low-K1 lithography

The use of low K1 lithography to extend Moores Law has been shown to have large implications for random logic design rules. In this work we are continuing the analysis of process control and design rule implications of low K1 lithographic systems to include highly optimized illumination and reticle enhancement conditions. Recent 248nm and 193nm lithography results have shown considerable improvements in two-dimensional pattern transfer linearity from optimized off-axis illumination. Due to the public unavailability of leading-edge layout rules (because of their extremely proprietary nature), we are applying our analysis to the simple lambda based design rule system of Mead and Conway. We analyze the impact of K1 and optimization method by comparing the (normalized) area of a typical SRAM bitcell redesigned according to these lambda based rules. The area of the bitcell strongly depends upon the design rules required for each enhancement technique and K1 factor to achieve a manufacturable cell. These area comparisons allow for easy viewing of the cost of pursuing different low K1 strategies. The results of this work are mainly generated from simulation but are backed by experimental verification from recent 193nm tool and process developments.

A Data-Model for a Technology and Simulation Archive

In this paper, we describe software aimed at achieving a significant reduction in the time required to develop new semiconductor technologies, by facilitating simulation sharing, and recognition and reuse of technology modules. We have created a technology and simulation archive based on the World-Wide Web (WWW) data-model. The WWW data-model is very flexible in capturing the wide variety of data formats of technology and simulation related information, and it proves to be sufficiently fast for frequent direct data retrieval by simulation tools.

Investigation of product design weaknesses using model-based OPC sensitivity analysis

Due to the challenging CD control and resolution requirements of future device generations, a large number of complex lithography enhancement techniques are likely to be used for random logic devices. This increased design, reticle, process and OPC complexity must be handled flawlessly by process engineers in order to create working circuits. Additionally, the rapidly increasing cost and cycletime of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have extended the capability of leading edge model-based OPC software to find and analyze process-limiting regions in real product designs. Specifically, we have implemented and verified software usefulness to find design-process limitations due to measured lens aberrations, as well as errors in focus, exposure or reticle CD control. We present results showing the applications and limitations of these new model-based analysis methods to discover process-design interaction errors in 90nm and 130nm patterning processes; and to propose design rule, process or OPC improvements to mitigate these errors.

Model-based design improvements for the 100-nm lithography generation

Due to the challenging design rule and CD control requirements of the 100 nm device generation, a large number of complex patterning techniques are likely to be used for random logic devices. The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non- idealities. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the 100 nm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle.

A Shared Architecture for a Dynamic TechnologySimulation Repository

In this paper, the design of a shared technology simulation repository is described. This system allows the download, archival, and simultaneous translation of equipment recipe and run data into a shared, revision controlled repository, as well as the automated generation of Technology Computer Aided Design (TCAD) input. Based on this system Computer Integrated Manufacturing (CIM) data and integrated circuit layout data can be combined to provide rapid technology optimization, enabling new methods of technology development.