Keiichi Maekawa

A Perpetuum Mobile 32bit CPU with 13.4pJ/cycle, 0.14μA sleep current using Reverse Body Bias Assisted 65nm SOTB CMOS technology

A 32-bit CPU which operates with the lowest energy of 13.4 pJ/cycle at 0.35V and 14MHz, operates at 0.22V to 1.2V and with 0.14μA sleep current is demonstrated. The low power performance is attained by Reverse-Body-Bias-Assisted 65nm SOTB CMOS (Silicon On Thin Buried oxide) technology. The CPU can operate more than 100 years with 610mAH Li battery.

Ultralow-voltage design and technology of silicon-on-thin-buried-oxide (SOTB) CMOS for highly energy efficient electronics in IoT era

Ultralow-voltage (ULV) operation of CMOS circuits is effective for significantly reducing the power consumption of the circuits. Although operation at the minimum energy point (MEP) is effective, its slow operating speed has been an obstacle. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for ultralow-power (ULP) electronics because of its small variability and back-bias control. These advantages of SOTB CMOS enable power and performance optimization with adaptive Vth control at ULV and can achieve ULP operation with acceptably high speed and low leakage. In this paper, we describe our recent results on the ULV operation of the CPU, SRAM, ring oscillator, and, other logic circuits. Our 32-bit RISC CPU chip, named “Perpetuum Mobile,” has a record low energy consumption of 13.4 pJ when operating at 0.35 V and 14 MHz. Perpetuum-Mobile micro-controllers are expected to be a core building block in a huge number of electronic devices in the internet-of-things (IoT) era.

0.39-V, 18.26-µW/MHz SOTB CMOS Microcontroller with embedded atom switch ROM

We present an ultra-low-power Microcontroller Unit (MCU) with an embedded atom switch ROM, which performs a 0.33-1.2 V operation voltage and 46.8-μA/MHz active current (or 18.26-μW/MHz active power). The MCU is fabricated by the hybrid of Silicon-On-Thin-Buried-oxide (SOTB) CMOS and bulk CMOS [1]. The SOTB CMOS with a body-bias voltage control realizes a high drivability up to 40-MHz operation at 0.54 V and small sleep power (0.628 μW), simultaneously.

A Silicon-on-Thin-Buried-Oxide CMOS Microcontroller with Embedded Atom-Switch ROM

The authors demonstrate an ultra-low-power microcontroller unit (MCU) with an embedded atom-switch ROM, which performs 0.39-V operation voltage and 18.26-pJ/cycle minimum active energy (or 18.26-μW/MHz minimum active power) at 14.3 MHz. The MCU is fabricated using an embedded atom-switch process with a hybrid silicon-on-thin-buried-oxide (SOTB) core and bulk I/O transistors. The atom switch is suitable for an ultra-low-voltage operation because of its high on/off conductance ratio. The SOTB CMOS with a body-bias voltage control realizes a high operation frequency of 40 MHz at 0.54 V and an ultra-low sleep power of 0.628 μW, simultaneously.

Si:C-S/D Engineering using Cascade C 7 H x Implantation Followed by Rapid Solid-Phase Epitaxy and Laser Annealing for nMOSFET with Highly-Strained and Low-Resistive S/D

Introduction Carbon doped source/drain (Si:C-S/D) is a quite attractive method for state-of-the-art CMOS devices as a booster technology[1-3]. In our previous work, we reported that high stress Si:C-S/D with high carbon concentration of substitution (CSi:C) formed by molecular carbon ion (C7Hx) implantation and solid-phase epitaxy (SPE) using non-melt laser annealing (LA) produces the large channel strain. It was also found that the combination of rapid thermal annealing (RTA) and LA in order to reduce the parasitic resistance of transistors relaxes the strain in Si:C layers[4]. The retrograde C profile with low temperature SPE has been also proposed as a countermeasure[5]. However further optimization should be necessary to form highly-strained channel and low-resistive Si:C-S/D. In this paper, we show the systematical investigation results about influences of the implanted ion-dose of P or As with various SPE conditions on the local stress at channel regions and sheet resistance (Rs) in Si:C layers. Moreover, it is demonstrated that precise control of cascade C7Hx implantation with RTA and LA is quite effective for improving transistor performances caused by highly-strained and low-resistive Si:C-S/D.

Analytical Approach for Enhancement of nMOSFET Performance with Si:C Source/Drain Formed by Molecular Carbon Ion Implantation and Laser Annealing

Introduction Strained Si channels have widely begun to be applied to state-of-the-art CMOS devices as a booster technology of the transistor performance. The carbon doped source/drain (Si:C-S/D) is one of the most attractive booster items for nMOSFETs, and it has been extensively investigated [1-3]. Two main approaches to fabricate Si:C-S/D have been proposed. One is the recess etching at S/D before selective vapor phase epitaxy using CVD systems. The other is solid phase epitaxy (SPE) of amorphous Si:C with carbon ion implantation. Recently, as a novel SPE technique for the Si:C-S/D formation, a combination of molecular carbon ion implantation and non-melt laser annealing was proposed [4]. Itokawa et al. showed that this metastable process provides the high carbon concentration of substitution (CSi:C) and capabilities for improving nMOSFET properties. In this paper, analytical approaches of the strained nMOSFET with Si:C-S/D are demonstrated. The channel strain induced by Si:C-S/D using molecular carbon ion implantation and leaser annealing was successfully measured by UV Raman spectroscopy for the first time. Using this particular technique, influences of the thickness of Si:C-S/D (TSi:C) and CSi:C on the local stress at the channel region were investigated. The improvement of the nMOSFET performance due to the local stress induced by Si:C-S/D was also confirmed.

Evaluation of change in drain current due to strain in 0.13-μm-node MOSFETs

1. fntroduction With the trend towards high integration of LSIs, the mechanical stress in a device has been increasing rapidly because of the high intrinsic stress in thin films. The stress developed in recent MOSFETs sometimes exceeds a few hundred mega pascals, which is high enough to cause a change in the transistor characteristics. That is, the mechanical stress can change the drain current of an 100-nm MOSFET more than llVo [1, 27. The change occurs as a result of the piezoresistance effect caused by residual stress in a silicon substrate [3]. It is thus very important to control the mechanical stress in 100-nm MOSFET devices in order to improve mechanical reliability and electronic performance. In this work, we clarified the strain (stress) sensitivity of drain current of a 0.l3-pm-node MOSFET, and developed a method for predicting the change in MOSFET drain current caused by thin-film processing.