Keng-Li Su

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Several emerging nonvolatile memories (NVMs) including phase-change RAM (PCRAM) [1–3], MRAM [4–5], and resistive RAM (RRAM) [6–8] have achieved faster operating speeds than embedded Flash. Among those emerging NVMs, RRAM has advantages in faster write time, a larger resistance-ratio (R-ratio), and smaller write power consumption. However, RRAM cells have large cross-die and within-die resistance variations (R-variations) and require low read-mode bitline (BL) bias voltage (VBL-R) to prevent read disturbance. This work proposes process/resistance variation-insensitive read schemes for embedded RRAM to achieve fast read speeds with high yields. An embedded mega-bit scale (4Mb), single-level-cell (SLC) RRAM macro with sub-8ns read-write random-access time is presented. Multi-level-cell (MLC) operation with 160ns write-ver-ify operation is demonstrated.

A low store energy, low VDDmin, nonvolatile 8T2R SRAM with 3D stacked RRAM devices for low power mobile applications

This work demonstrates the first fabricated macro-level RRAM-based nonvolatile SRAM (nvSRAM) that use a new 8T2R (Rnv8T) cell to achieve fast NVM storage and low VDDmin read/write operations. The Rnv8T cell uses two fast-write low-current RRAM devices, 3D stacked over the 8T, to achieve low store energy with a compact cell area (1.6x that of a 6T cell). A 2T RRAM-switch provides both RRAM control and write-assist functions. This write assist feature enables Rnv8T cell to use read favored transistor sizing against read/write failure at a lower VDD. The fabricated 16Kb Rnv8T macro achieves the lowest store energy and R/W VDDmin (0.45V) than other nvSRAM and “SRAM+NVM” solutions.

Fast-Write Resistive RAM (RRAM) for Embedded Applications

Especially for microcontroller and mobile applications, embedded nonvolatile memory is an important technology offering to reduce power and provide local persistent storage. This article describes a new resistive RAM device with fast write operation to improve the speed of embedded nonvolatile memories.

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes

ReRAM is a promising next-generation nonvolatile memory (NVM) with fast write speed and low-power operation. However, ReRAM faces two major challenges in read operations: 1) low read yield due to wide resistance distribution and 2) the requirement of accurate bit line (BL) bias voltage control to prevent read disturbance. This study proposes two process-variation-tolerant schemes for current-mode read operation of ReRAM: parallel-series reference-cell (PSRC) and process-temperature-aware dynamic BL-bias (PTADB) schemes. These schemes are meant to improve the read speed and yield of ReRAM, while taking read disturbance into consideration. PSRC narrows the reference current distribution to achieve high read yield against resistance variation. PTADB achieves small fluctuations in BL bias voltage to prevent read disturbance, while providing rapid BL precharge speeds. This study fabricated a 4-Mb ReRAM macro to confirm the effectiveness of the proposed schemes for both SLC and MLC operations. The fastest sub-8-ns (7.2 ns) read-write random access time among megabit scaled embedded NVM macros has been demonstrated.

ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing

This study proposes an RC-filtered stress-decoupled (RCSD) 4T2R nonvolatile TCAM (nvTCAM) to 1) suppress match-line (ML) leakage current from match cells (IML-M), 2) reduce ML parasitic load (CML), 3) decouple NVM-stress from wordlength (WDL) and IML-MIS. RCSD reduces NVM-stress by 7+x, and achieves a 4+x improvement in speed-WDL-capacity-product. A 128×32b RCSD nvTCAM macro was fabricated using HfO ReRAM and an 180nm CMOS. This paper presents the first ReRAM-based nvTCAM featuring the shortest (1.2ns) search delay (TSD) among nvTCAMs with WDL≥32b.

A ReRAM integrated 7T2R non-volatile SRAM for normally-off computing application

This study demonstrates a new 7T2R nonvolatile SRAM (nvSRAM) with 3D ReRAM stacked structure for normally-off computing application. With this structure, the fully performance of SRAM can work well in active mode, and reduce the leakage current in power-off mode. High performance HfOx based ReRAM is used for high speed storage element and exhibits an instant-on characteristic. The present 7T2R nvSRAM cell includes a 1T2R RRAM (1 transistor/2 resistive memory) cell and a 6T SRAM circuit, which is low area penalty and achieve the nvSRAM function. The write margin is improved over 1.03x and 1.37x larger than that of 6T SRAM and 6T2R nvSRAM. The access time and read/write power consumption in 7T2R nvSRAM is better than that of 8T2R structure. Finally, a 16 Kb macro was fabricated with a 0.18 μm TSMC FEOL and ITRI BEOL. According to the measurement result, the VDDmin can be low down to 0.7 V and access time can be fast as 8.3 ns without pad delay. The data storage time is only 10 ns for SET and RESET in the ReRAM cell.

Design optimization in write speed of multi-level cell application for phase change memory

Design optimization to improve write speed of phase change memory is shown achievable by using a physical yet analytical compact PCM model. Our simulation results suggested that the write speed of continuous pulse programming scheme can be optimized and is superior to slow quenching scheme for multi-level cell application.

A nonvolatile look-up table using ReRAM for reconfigurable logic

This study demonstrated a nonvolatile look-up table (nvLUT) that involves using resistive random access memory (ReRAM) cells with normally-off and instant-on functions for suppressing standby current. Compared with the conventional static random access memory (SRAM)-magnetoresistive random-access memory (MRAM)-hybrid LUTs the proposed ReRAM-based two-input nvLUT circuit decreases the number of transistors and the area of nvLUT by 79% and 90.4%, respectively. The areas of the two- and three-input ReRAM nvLUTs are 11.5% and 74.2% smaller than the other MRAM-based two-input and PCM-based three-input LUTs, respectively. Because of the low current switching and high R-ratio characteristics of ReRAM, the proposed ReRAM-based nvLUT achieves 24% less power consumption than that of SRAM-MRAM-hybrid LUTs. The functionality of the fabricated adder of the three-input ReRAM nvLUT was confirmed using an HfOx-based ReRAM and a 0.18-μm complementary metal-oxide semiconductor with a delay time of 900 ps.

Electrical characterization of through silicon vias (TSVs) with an on chip bus driver for 3D IC integration

In this study, an on chip bus driver TEG (test element group) has been developed for the data transmission performance at TSVs for 3D IC integration. The on chip bus driver TEG consists of transceiver (TX), receiver (RX) and TSV group which has 2, 4 and 8 TSVs for the analysis of the TSV transmission performance with different load effects which are caused by different number (2, 4, and 8) of chip stack (each chip is with one TSV). This chip has been made by TSMCs 0.18μm process (FEOL) and ITRIs BEOL process. The square chip area is 1.69mm2 and power supply voltage is 1.8V with 30μm diameter TSVs on 30μm pitch and 100μm depth. Finally, a design guide line and a test tool will be proposed with the present on chip bus TEG.

4-Mb SPI Flash Compatible Phase-Change Memory

A 4-Mb with SPI serial interface phase-change memory which is completely compatible with the traditional SPI flash memory is implemented in this study. The peripheral circuit is much simpler than flash memory. The 512 Kb sector erase time is less than 7 ms while the 4 Mb bulk erase time is 80 ms only.