Martin Städele

20 nm tri-gate SONOS memory cells with multi-level operation

Fast programmable tri-gate oxide-nitride-oxide (ONO) transistor memory cells with sub-10 nm fin width and gate lengths down to L/sub G/ = 20 nm have been fabricated and successfully operated in multi-level mode for the first time. In spite of thick tunnel oxides required for reliable retention, the devices were optimized for either two level operation with very short program and erase times of t/sub P/ = 20 /spl mu/s and t/sub E/ = 1 ms and threshold voltage shifts of /spl Delta/V/sub th/ /spl sim/ 3 V or for multi-level mode with t/sub PE/ = 2 ms and /spl Delta/V/sub th/ < 4 V. In addition, a simple 6F/sup 2/ NOR array scheme is proposed that meets the large /spl Delta/V/sub th/ shift specific read and write disturb requirements thus allowing for a cost effective high density 3F/sup 2//bit nonvolatile memory for data storage applications.

Full band approach to tunneling in MOS structures

Using atomistic quantum mechanical tight-binding (TB) methods that include the full band structure, we study electron tunneling through three-dimensional models of n/sup +/-Si/SiO/sub 2//p-Si capacitors with thicknesses between 0.7 and 4.4 nm. We find that the microscopic oxide structure influences transmission coefficients and tunnel currents significantly. The best agreement with experimental current-thickness and current-voltage data is obtained for a model derived from the /spl beta/-cristobalite polytype of SiO/sub 2/ that has a fairly small conduction band mass of 0.34 m/sub 0/. Standard approximate effective mass-based methods reproduce the TB results only if an energy and oxide thickness dependence of the mass parameter is introduced.

Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

Abstract Drift-diffusion simulations have been carried out to investigate the design space for n-channel fully depleted (FD) SOI transistors with undoped channels and midgap gates in the 25–50 nm gate length regime. Gate length, Si-body thickness, source drain doping concentration profile, and spacer width have been varied. Provided that the gate length is larger than 3–4 times the Si-body thickness, we find that the high performance targets of the International Technology Roadmap for Semiconductors can be fulfilled for many different parameter combinations. This means that FD SOI is a suitable technology for devices with feature sizes on this length scale.

Resonant electron tunneling through defects in ultrathin SiO2 gate oxides in MOSFETs

To analyze defect-assisted elastic tunneling currents through ultrathin SiO2 gate oxides in metal-oxide semiconductor field-effect transistors (MOSFETs), we have combined semiempirical microscopic tight-binding calculations with full-band Monte Carlo transport simulations. Two prototypical devices with channel lengths of 50 and 90 nm were considered. We find that defects having an area density larger than 1011 cm−2 can enhance tunneling currents by several orders of magnitude in both devices. Resonant tunneling effects are predicted to be more pronounced for thicker oxides. For oxides thinner than 2 nm, hot electrons are unlikely to dominate gate leakage currents in the presence of defects.

CMOS based arrays of nanogap devices for molecular electronics

In this paper we present a novel nanogap device architecture for molecular electronics which is fully CMOS compatible and non-invasive to the contacted self-assembled monolayer. The device exhibits precise control over the electrode spacing. Single cells as well as arrays with electrode distances of 2.5 nm have been realized and characterized in terms of basic functionality and yield. Simulations have revealed scalability for feature sizes down to the ten nanometer regime.

Simulation of High-K Tunnel Barriers for Nonvolatile Floating Gate Memories

Replacing silicon dioxide tunnel dielectrics in nonvolatile floating gate memories by high-K materials may pave the way to continued scaling of state of the art flash memories. To evaluate the requirements for barrier height, programming voltages and injection speed, we have calculated WKB currents through single layer and multilayer high-K based dielectrics. For a single layer minimal barrier height of about 2eV, limited by thermionic current, we find Fowler-Nordheim programming voltages of about 7-9V. In order to further reduce the voltage or enhance the injection tunnel current, symmetric triple layers of sequence low-K/highK/low-K are proposed. Asymmetric structures are also briefly discussed.

Full band Monte Carlo simulations of high-field electron transport in wide band-gap semiconductors

We perform ab initio band structure calculations within density functional theory using an exact exchange formalism and a local density approximation for correlations. Ensemble Monte Carlo simulations consider all relevant scattering mechanisms including a realistic impact ionization rate. This full-band ensemble Monte Carlo method is applied to study the high-field electron transport. Results can be given for the total electron–phonon scattering rate, the drift velocity, the mean kinetic energy, the valley occupations and the ionization coefficient. We show here exemplary results for the wide band-gap materials ZnS and GaN.

Tunneling through Thin Oxides—New Insights from Microscopic Calculations

In this paper, we summarize our recent efforts to analyze transmission probabilities of extremely thin SiO2 gate oxides using microscopic models of Si[100]-SiO2-Si[100] heterojunctions. We predict energy-dependent tunneling masses and their influence on transmission coefficients, discuss tunneling probabilities and analyze effects arising from the violation of parallel momentum conservation. As an application of the present method, gate currents in short bulk MOSFETs are calculated, including elastic defect-assisted contributions.

Full 3D Process and Device Simulation for FinFET optimization

Based on a state-of-the-art 3D process and device simulation framework, we present an extensive analysis of the impact of FinFET process parameters on the device characteristics. The results compare well with the available experimental data.

Atomistic tight-binding calculations for the investigation of transport in extremely scaled SOI transistors

This paper reviews the basic methodology and highlights advantages and recent applications of atomistic tight-binding calculations for the investigation of carrier transport in extremely scaled SOI transistors. The calculations yield numerous insights into direct and defect-assisted gate oxide tunneling, source-drain transport and tunneling, subband coupling, and carrier quantization in ultrathin-body devices with (possibly strained) Si and SiGe channels. The present results are in very good agreement with the available experimental data and document limitations of the standard effective-mass-based schemes.