M. Ramon

Impact of Deposition and Annealing Temperature on Material and Electrical Characteristics of ALD HfO2

Hafnium oxide (HfO 2 ) is one of the most promising high-k materials to replace SiO 2 as a gate dielectric. Here we report material and electrical characterization of atomic layer deposition (ALD) hafnium oxide and the correlations between the results. The HfO2 films were deposited at 200, 300, or 370°C and annealed in a nitrogen ambient at 550, 800, and 900°C. Results indicate that deposition temperature controls both the material and the electrical properties. Materials and electrical properties of films deposited at 200°C are most affected by annealing conditions compared to films deposited at higher temperatures. These films are amorphous as deposited and become polycrystalline after 800°C anneals. Voids are observed after a 900°C anneal for the 200°C deposited films. The 200°C deposited films have charge trapping and high leakage current following anneals at 900°C. The 300°C deposited films have lower chlorine content and remain void-free following high-temperature anneals. These films show a thickness-dependent crystal structure. Annealing the films reduces leakage current by four orders of magnitude. Finally, films deposited at 370°C have the highest density, contain the least amount of impurities, and contain more of the monoclinic phase of HfO 2 than those deposited at 300 and 200°C. The best electrical performance was obtained for films deposited at 370°C.

Impact of titanium addition on film characteristics of HfO2 gate dielectrics deposited by atomic layer deposition

The impact of 8-to45-at.% Ti on physical and electrical characteristics of atomic-layer-deposited and annealed hafnium dioxide was studied using vacuum-ultraviolet spectroscopic ellipsometry, secondary ion mass spectroscopy, transmission electron microscopy, atomic force microscopy, x-ray diffraction, Rutherford backscattering spectroscopy, x-ray photoelectron spectroscopy, and x-ray reflectometry. The role of Ti addition on the electrical performance is investigated using molybdenum (Mo)-gated capacitors. The film density decreases with increasing Ti addition. Ti addition stabilizes the amorphous phase of HfO2, resulting in amorphous films as deposited. After a high-temperature annealing, the films transition from an amorphous to a polycrystalline phase. Orthorhombic Hf–Ti–O peaks are detected in polycrystalline films containing 33-at.% or higher Ti content. As Ti content is decreased, monoclinic HfO2 becomes the predominant microstructure. No TiSi is formed at the dielectric/Si interface, indicating fil...

Physical and Electrical Characteristics of HfO2 Gate Dielectrics Deposited by ALD and MOCVD

Film characteristics of HfO 2 gate dielectrics formed on Si(100) by atomic layer deposition (ALD) or metallorganic chemical vapor deposition (MOCVD) were investigated by atomic force microscopy, transmission electron microscopy, secondary ion mass spectroscopy (SIMS), X-ray reflectometry, ellipsometry, and electrical measurements. HfCl 4 and water were the precursors used for ALD HfO 2 deposition at 300 and 370°C, whereas C 1 6 H 3 6 HfO 4 was used for MOCVD deposition at 550 and 650°C. Film thickness increases linearly with time for both deposition techniques. The ALD and MOCVD films have comparable density. MOCVD thin films are polycrystalline, while the 300°C deposited ALD HfO 2 are amorphous. The 370°C deposited ALD HfO 2 are polycrystalline. SIMS analysis indicated chlorine and carbon are the major contaminants in ALD and MOCVD HfO 2 films, respectively. Electrical properties of ALD and MOCVD HfO 2 films were examined using metal oxide silicon capacitors. Well-behaved capacitance-voltage and leakage current-voltage characteristics were obtained for both types of films. ALD films have slightly higher capacitance and comparable leakage when compared to MOCVD films. Room temperature and 105°C stressing of the capacitance-voltage curves showed a significant shift in the capacitance-voltage curve indicating that charge trapping was observed for all films with the 650°C deposited MOCVD showing the largest capacitance-voltage shift. Unlike MOCVD films, the capacitance-voltage characteristics of ALD films remain well behaved after stressing.

Characteristics of Mixed Oxides and Nanolaminates of Atomic Layer Deposited HfO2 – TiO2 Gate Dielectrics

Thin film characteristics of HfO 2 -TiO 2 mixed oxides and nanolaminates formed by atomic layer deposition were studied using transmission electron microscopy (TEM), atomic force microscopy, X-ray reflectometry, and metal oxide semiconductor capacitors. The role of HfO 2 underlayer and the impact of the location of TiO 2 in HfO 2 -TiO 2 gate dielectrics were also investigated. Some differences in grain-size distribution were observed between mixed oxides and nanolaminates. In mixed oxide films, the grains became smaller and clustered together to form elongated structures as TiO 2 is added. For nanolaminates, the grains became smaller than HfO 2 but they did not form elongated structures. Cross-sectional TEM showed that as-deposited HfO 2 -TiO 2 films were amorphous with a thinner interfacial layer than that of HfO 2 . After annealing, films became rougher, with an increase in interfacial layer thickness. A minimum of 20 cycles of HfO 2 (∼10 A) was needed as an underlayer to obtain well-behaved electrical characteristics. Capacitance-voltage stressing performed on these films showed improved charge trapping behavior for mixed oxide and nanolaminate structures.

BTI characteristics and mechanisms of metal gated HfO/sub 2/ films with enhanced interface/bulk process treatments

Significant deviations in BTI characteristics for metal gate HfO/sub 2/ films compared to silicon oxide based films prove that conventional reliability models based on SiO/sub 2/ films can no longer be directly applied to HfO/sub 2/ based MOSFETS. This study shows the use of conventional accelerated reliability testing in the Fowler-Nordheim tunneling regime to extrapolate time to failure at operating voltages (direct tunneling regime) overestimates device lifetimes. Additionally, unlike conventional gate oxides, the slope of /spl Delta/V/sub t/ versus time (or the rate of charge trapping) in HfO/sub 2/ MOSFETS is dependent on stress voltage. The HfO/sub 2/ based metal gated nMOSFETS show poor PBTI characteristics and do not meet the 10 year lifetime criterion for threshold voltage stability. On the other hand, HfO/sub 2/ based pMOSFETS show superior NBTI behavior and meet the 10 year lifetime criterion. These results are contrary to the observations with conventional gate dielectrics. This paper explores the anomalous charge trapping behavior and provides a comprehensive study of the PBTI characteristics and recovery mechanisms in metal gated HfO/sub 2/ films.

Performance of super-critical strained-Si directly on insulator (SC-SSOI) CMOS based on high-performance PD-SOI technology

This paper describes the performance of multiple-V/sub T/, Triple-gate oxide SC-SSOI CMOS realized with Freescales high-performance silicon-on-insulator (HiPerMOS-SOI) and SOITECs advanced wafer-bonding technology. The thermal stability of wafer-bonded strained substrate, the beneficial impact of biaxial strain on gate-leakage and SC-SSOI enhanced SRAM bitcell operation are demonstrated for the first time. In-addition, the important scaling issues due to parasitic resistance and channel strain engineering are identified.

Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance

Using a novel fluorinated TaxCy/high-k gate stack, we show breakthrough device reliability and performance improvements. This is a critical result since threshold voltage instability may be a fundamental problem and performance degradation for high-k is a concern. The novel fluorinated gate stack device exceeds the PBTI and NBTI targets with sufficient margin and has electron mobility comparable to the best polySi/SiON device on bulk Si reported so far

Microstructure modified HfO/sub 2/ using Zr addition with Ta/sub x/ C/sub y/ gate for improved device performance and reliability

For the first time we report on the development of a novel hafnium zirconate (HfZrO_x) gate dielectric with a Ta_xC_y metal gate. Compared to HfO₂, the new HfZrO_x gate dielectric showed: (1) higher transconductance, (2) less charge trapping, (3) higher drive current, (4) lower NMOS V_t, (5) reduced C-V hysteresis, (6) lower interface state density, (7) superior wafer-level thickness uniformity, and (8) longer PBTI lifetime. We attribute these improvements to a microstructure that is modified by addition of Zr to HfO₂

Threshold voltage instability and plasma induced damage of polySi/HfO/sub 2/ devices - positive impact of deuterium incorporation

Device instability is one of the most challenging issues to implement High-K gate dielectric. Incorporation of deuterium during the ALD process effectively improves the interface quality that enhances High-K device stability and reliability. Compared to H/sub 2/O processed HfO/sub 2/ devices, devices with D/sub 2/O processing result in a significantly smaller Vt shift after constant voltage stressing at room temperature and at 125/spl deg/C under NBTI/PBTI conditions, as well as a longer CHCI lifetime. This process is independent of transistor process integration and is relatively low cost. It has the potential to become an industry standard if ALD High-K gate dielectric processing is the final choice.

Mechanism of Gm degradation and comparison of Vt instability and reliability of HfO/sub 2/, HfSiO/sub x/ and HfAlO/sub x/ gate dielectrics with 80 nm poly-Si gate CMOS

To achieve a lower gate leakage in high speed devices at the same equivalent oxide thickness, a major thrust is to replace the SiO/sub 2/ with a thicker dielectric that has a higher dielectric constant. Recently, there has been much interest in hafnium dioxide as a potential high-k gate dielectric as presented in E. P Gusev et a. (2001), B. Barlage et al. (2001), G. Wilk et al. (2001), C. Hobbs et al. (2001), W. Zhu et al. (2001), W. Qi et al. (2000) and B. Lee et al. (1999) due to its high permittivity. However, the polycrystalline microstructure may be undesirable. In order to increase the crystallization temperature, SiO/sub 2/ or Al/sub 2/O/sub 3/ are added to HfO/sub 2/ to form Hf silicates atid Hf aluminates. A systematic study to compare the device characteristics of these three major candidates is needed. In this work, we have compared them in terms of the key challenges of high-K devices such as Gm degradation, Vt instability, and reliability, in devices fabricated with a conventional CMOS process technology according to A. Perera et al. (2000).