Melina Lofrano

3D stacking induced mechanical stress effects

In this work the effects of 3D stacking technology on the performance of devices are systematically studied. For this study a special chip consisting of a number of stress sensors and vertical interconnect loops was designed and manufactured in 65 nm technology. Local variations of stress with a magnitude of up to 300 MPa are detected at different locations along the chip and are being characterized using finite element modeling and micro-Raman spectroscopy measurements.

Chip package interaction (CPI): Thermo mechanical challenges in 3D technologies

The residual stresses generated during different processing steps and during thermal cycling of 3D stack packages, mimicking its service life, are quantified by Finite Element Modeling (FEM) together with measurements of dedicated FET arrays used as CPI sensors. Thermo-mechanical deformation of the package can be directly transferred to the Cu/low-k interconnect, inducing large local stresses to drive interfacial crack formation and propagation. The test vehicle used in this work is an imecs proprietary logic CMOS IC on top of which a commercial DRAM is stacked. Different test structures contained in the chip, allow monitoring thermo-mechanical stresses and electrical characteristics of TSVs and micro-bumps. It is shown that FET current shifts can be used to measure the stress in the surface of the chip. The use of standard FEM approach is insufficient to simulate the CPI due to the large dimensional difference between the packaging and interconnects structures. Due to size and speed limitations of commercial computers, a 3D thermo mechanical model of a 3D package cannot contain all the details from the package and at the same time simulate the small structures such as metal and dielectric layers in the BEOL. For this reason, multi-scale simulations are the best choice for identifying the critical regions of the package where high stresses and/or delamination failures are expected to occur. We have shown the methodology to follow to study the CPI.

Optimal T-support anchoring for bar-type BAW resonators

This paper reports on an optimal support anchoring for bar-type BAW resonators. We demonstrate both theoretically and experimentally the implementation of long (in terms of acoustic wavelength) T-supports without compromising neither on the Q-factor nor on the electromechanical (pull-in) stability of the resonator. Compared to the more common straight supports, these long T-supports provide rigidity for displacements in one direction combined with low stiffness in the other two directions, thus offering more freedom in the structural design, as well as potential for thermal “manipulation”, e.g., insulation.

Degradation and failure analysis of copper and tungsten contacts under high fluence stress

The reliability of Cu and W contacts under high fluence stress mimicking source/drain contacts in the on-state of a transistor is evaluated. We use Kelvin structures to study the contact degradation and to determine the lifetime as a function of voltage and temperature. Failure analysis reveals significant damage created in the proximity of the contacts. It is concluded that not electromigration alone, but also Joule heating of the contact and the contact interfaces triggers failure.

Study of void formation kinetics in Cu interconnects using local sense structures

A test structure that allows the study of void formation kinetics during electromigration is proposed and characterized. Compared to a standard single-via electromigration test structure voltage-senses are placed near the via. This allows monitoring resistance changes before final void formation, while the void formation process is not affected. Part of the samples show single void formation, while for other samples, multiple voids are formed. For the single void case, a model is proposed to calculate void-depth as a function of time. Initially, voids grow faster and this growth slows down towards the end of the void formation process. Estimated velocities during void formation are in the same order of magnitude compared to literature results of drift velocities during void growth. Cases where multiple voids are formed show that voids which initially form further away from the via stop growing upon formation of a void closer to the via.

Electromigration and stress-induced-voiding in dual damascene Cu/low-k interconnects: a complex balance between vacancy and stress gradients

The influence of residual vacancy concentrations and stress gradients on electromigration both in the metal layer below and above copper vias with a diameter of 90nm integrated in low-k materials has been investigated. Variations in stress gradients and vacancy concentrations were created by applying different post-plating anneal conditions. The impact of these variations was quantified based on high temperature storage tests both at the optimum stress-induced-voiding temperature and around the copper stress free temperature. By linking the results from these high temperature storage tests to electromigration data, we observe residual vacancy concentrations contribute more to upstream electromigration, while downstream electromigration is more vulnerable to residual stress gradients.

Raman spectroscopy study of stress in 3D-stacked chips and correlation with FEM and electrical measurements

Micro-Raman spectroscopy (μRS), finite element modelling, and electrical measurements of transistors used as stress-sensors, are used to study stress in a 3D-stacked IC. It is shown that the combination micro-bumps/underfill causes large stress variations in the silicon. Correlation of the three techniques shows that the effect of the different stress components and of X-sectioning on stress reduction has to be taken into account when performing μRS measurements on the X-section of a sample.

A CMOS-compatible 24MHz poly-SiGe MEMS oscillator with low-power heating for frequency stabilization over temperature

MEMS based timing devices have been proposed as an alternative to Quartz systems for certain applications. Through using an oven-controlled system it is possible to stabilize the frequency response of such a MEMS system over a large ambient temperature range. This work presents a BAW MEMS resonator in poly-SiGe which achieves significantly lower power consumption for frequency stabilization over temperature through Joule heating than for a similar system in SOI, while showing promising phase noise performance in an oscillator setup. Since the poly-SiGe resonator can be processed on top of standard CMOS, this enables the possibility of full integration of an Oven-Controlled MEMS Oscillator.

Time and temperature dependence of early stage Stress-Induced-Voiding in Cu/low-k interconnects

The time and temperature dependence of Stress-Induced-Voiding below and in copper VIAs with a diameter of 80nm integrated in a k=2.5 material was studied. The focus was on the early phase of the voiding process. To accelerate the degradation, test structures with big metal plates below and/or above the VIA were used. We found two degradation mechanisms in which one dominated below and the other dominated above a certain temperature. The first mechanism has an activation energy of 0.9eV and is the result of interface-diffusion driven by a stress-gradient. This mechanism was more pronounced below the VIA, but was significant in the VIA as well. The second mechanism has an activation energy of 1.2eV, which is argued to be driven by grain boundary diffusion due to a vacancy gradient in and above the VIA. To explain both mechanisms, an addition to the traditional stress-creep model is proposed and fits our data well. Additionally, it is discussed that VIAs connected to the center of big metal plates above and below the VIA are less susceptible to SIV compared to VIAs connected to line ends either below or on top of the VIA. We support our argumentation and analytical modeling with Finite Element Modeling.

Intrinsic study of current crowding and current density gradient effects on electromigration in BEOL copper interconnects

The intrinsic effects of current crowding and current density gradients on electromigration in back end of line copper interconnects have been investigated using a simple single layer test structure, where the electromigration performance of standard straight structures is compared to structures with a 90° angle. Using finite element modeling, it is demonstrated that locally higher current crowding and current density gradients are indeed present in these angled structures. As electromigration lifetimes are comparable between the straight and the angled structures and no void formation is observed in or close to the angle, we conclude that the intrinsic impact of current crowing and current density gradients in via-electromigration is negligible.