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Dive into the research topics where Michelle L. Steen is active.

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Featured researches published by Michelle L. Steen.


Journal of Vacuum Science & Technology B | 2005

Effect of plasma interactions with low- κ films as a function of porosity, plasma chemistry, and temperature

Marcus A. Worsley; Stacey F. Bent; Stephen M. Gates; Nicholas C. M. Fuller; Willi Volksen; Michelle L. Steen; Timothy J. Dalton

Integration of new low-κ interlayer dielectrics (ILD) with current damascene schemes is a continuing issue in the microelectronics industry. During integration of the ILD, processing steps such as plasma etching, resist strip, and chemical-mechanical planarization are known to chemically alter a layer of the dielectric. Here, porous organosilicate glass (OSG) ILD films, which—according to the 2004 edition of the International Technology Roadmap for Semiconductors—are projected for use in the 65 and 45 nm nodes, are investigated. spectroscopic ellipsometry, x-ray photoelectron spectroscopy, and Fourier transform infrared spectroscopy are used to characterize the modified layer of the ILD after exposure to O2 or H2 resist strip plasmas. The effects of the two types of plasma etch chemistries on the formation of the modified layer were found to differ significantly. These effects include both the degree of modification (i.e., chemical composition) and depth of the modified layer. A key difference between the...


symposium on vlsi technology | 2005

Role of oxygen vacancies in V FB /V t stability of pFET metals on HfO 2

E. Cartier; F. R. McFeely; Vijay Narayanan; P. Jamison; Barry P. Linder; M. Copel; Vamsi Paruchuri; V.S. Basker; Richard Haight; D. Lim; R. Carruthers; T. Shaw; Michelle L. Steen; Jeffrey W. Sleight; J. Rubino; H. Deligianni; Supratik Guha; Rajarao Jammy; Ghavam G. Shahidi

We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V/sub FB/ can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V/sub FB//V/sub t/-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V/sub FB//V/sub t/. The results indicate that V/sub FB//V/sub t/ control remains a formidable processing challenge with high workfunction metals on HfO/sub 2/.


symposium on vlsi technology | 2005

Role of oxygen vacancies in V/sub BF//V/sub t/ stability of pFET metals on HfO/sub 2/

E. Cartier; F. R. McFeely; Vijay Narayanan; P. Jamison; Barry P. Linder; M. Copel; Vamsi Paruchuri; V.S. Basker; Richard Haight; D. Lim; R. Carruthers; T. Shaw; Michelle L. Steen; J. Sleight; J. Rubino; H. Deligianni; Supratik Guha; Rajarao Jammy; Ghavam G. Shahidi

We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V/sub FB/ can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V/sub FB//V/sub t/-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V/sub FB//V/sub t/. The results indicate that V/sub FB//V/sub t/ control remains a formidable processing challenge with high workfunction metals on HfO/sub 2/.


Proceedings of SPIE | 2004

High-performance thick copper inductors in an RF technology

Kunal Vaed; William S. Graham; Michelle L. Steen; Jae-Eun Park; Robert A. Groves; Richard P. Volant; Ronald W. Nunes; James Vichiconti; Kenneth J. Stein; David C. Ahlgren

With the emergence of wired and wireless communication technologies, on-chip inductors find applications in a variety of high performance radio frequency (RF) circuits. In this work, we present two approaches for high-performance copper inductors in an RF technology. In the first approach (Type I), we lower ohmic losses to realize a high Q-factor. This is achieved by using, for the first time in a manufacturable technology, 4 μm thick copper spirals along with a 4 μm thick copper underpass on high-resistivity substrates (75 Ω-cm). The underpass is connected to the spirals with a 4 μm tall copper via, which lowers spiral to underpass capacitance. For further lowering the capacitive losses, an additional 6.1 μm thick interlayer dielectric separates the underpass from the substrate. In the second approach (Type II), we utilize a novel one-mask CMOS-compatible micromachining scheme to eliminate substrate losses. This is achieved by completely removing the silicon substrate from directly below the inductors. For a 1.1nH inductor, peak-Q shows an impressive two-fold improvement from 26.6 at 3.8 GHz for Type I inductor to 52.8 at 8.2 GHz for Type II inductor after silicon micromachining. The resonant frequency increases from 18 GHz to 27 GHz after substrate micromachining.


IEEE Electron Device Letters | 2004

CVD rhenium and PVD tantalum gate MOSFETs fabricated with a replacement technique

James Pan; Don Canaperi; R. Jammy; Michelle L. Steen; John G. Pellerin; Ming-Ren Lin

This letter reports the first replacement metal gate MOSFETs with chemical vapor deposition (CVD) Rhenium (Re), and physical vapor deposition (PVD) Tantalum (Ta) as the stacked gate electrode. Transistors with PVD Ta electrode are fabricated with a replacement and a nonself-aligned method for comparison. Our data show that CVD Re can be implemented as a gate electrode material for MOS transistors. The CVD Re process has the advantage of reducing the plasma and radiation damages to the gate oxide. A thick layer of PVD Ta covering a thin layer of CVD Re forms the stacked gate structure and makes the metal chemical-mechanical polishing feasible.


symposium on vlsi technology | 2005

Role of oxygen vacancies in V/sub FB//V/sub t/ stability of pFET metals on HfO/sub 2/

E. Cartier; F. R. McFeely; Vijay Narayanan; P. Jamison; Barry P. Linder; M. Copel; Vamsi Paruchuri; V.S. Basker; Richard Haight; D. Lim; R. Carruthers; T. Shaw; Michelle L. Steen; J. Sleight; J. Rubino; H. Deligianni; Supratik Guha; Rajarao Jammy; Ghavam G. Shahidi

We demonstrate experimentally that the flatband/threshold voltages (V/sub FB//V/sub t/) of pFET metal gates are strongly dependent on the post-deposition annealing conditions of the gate stacks. By varying the temperature and the O/sub 2/ partial pressure during post-deposition N/sub 2//O/sub 2/ and/or forming gas annealing (FGA) with Re, Ru and Pt, the gate stack V/sub FB/ can change by as much as 750 mV. However, using Re as an example, it is shown that conditions can be optimized and V/sub FB//V/sub t/-tuning for pFETs can be achieved for aggressively scaled stacks. It is proposed that charge transfer from oxygen vacancies to the gate electrode, possible only for high workfunction metal gates, leads to the formation of a dipole layer near the gate which can shift V/sub FB//V/sub t/. The results indicate that V/sub FB//V/sub t/ control remains a formidable processing challenge with high workfunction metals on HfO/sub 2/.


Archive | 2003

Silicon chip carrier with conductive through-vias and method for fabricating same

Daniel C. Edelstein; Paul S. Andry; Leena Paivikki Buchwalter; Jon A. Casey; Sherif A. Goma; Raymond Robert Horton; Gareth G. Hougham; Michael Lane; Xiao Hu Liu; Chirag S. Patel; Edmund J. Sprogis; Michelle L. Steen; Brian R. Sundlof; Cornelia K. Tsang; George Frederick Walker


Archive | 2003

Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory

Hendrik F. Hamann; Chung Hon Lam; Michelle L. Steen; H.-S.P. Wong


Archive | 2005

High performance CMOS circuits, and methods for fabricating the same

John C. Arnold; Glenn A. Biery; Alessandro Callegari; Tze-Chiang Chen; Michael P. Chudzik; Bruce B. Doris; Michael A. Gribelyuk; Young-Hee Kim; Barry P. Linder; Vijay Narayanan; J. Newbury; Vamsi Paruchuri; Michelle L. Steen


Archive | 2003

Deep filled vias

Panayotis C. Andricacos; Emanuel I. Cooper; Timothy J. Dalton; Hariklia Deligianni; Daniel Guidotti; Keith T. Kwietniak; Michelle L. Steen; Cornelia K. Tsang

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