Ranjan Rajoo

The mechanics and impact of hygroscopic swelling of polymeric materials in electronic packaging

A reliable technique for characterising the hygroscopic swelling of materials has been developed and used to characterise a number of packaging materials. The hygro-swelling of these materials, though varing in magnitude, exhibits a common behavior in that it increases with temperature and decreases sharply across T/sub g/. Using this data, hygroscopic stress modeling was performed on leaded and substrate based packages. The hygroscopic stress induced through moisture conditioning was found to be significant compared to the thermal stress during solder reflow. Hygroscopic stress in over-molded wire bond PBGA & molded flip chip PBGA was found to be 1.3 to 1.5 times that of thermal stress. Hygroscopic swelling of the underfill in flip chip PBGA was found to be the main failure driver during autoclave test. Autoclave performance of flip chip PBGA package assembled with different underfills & chips was analysed. Excellent correlation was found between autoclave performance and the hygroscopic swelling characteristics of the underfills.

Drop Impact: Fundamentals and Impact Characterisation of Solder Joints

This paper presents a summary of the fundamental theories behind board level drop impact covering the dynamics of drop impact assembly, dynamics of PCB, as well as interconnection stress. This is followed by a comprehensive study of the fracture characteristics of solder interconnections under high-speed impact using a newly developed Micro Impactor which provides both the fracture strength as well as fracture energy of impact. The test matrix consists of 5 solder alloys, 4 pad finishing, 3 thermal histories, and 2 solder mask designs forming a total of 120 combinations. The test has highlighted weakness in NSMD design and caution on SnAgCu solder when used in drop impact application

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10mm × 10mm × 0.4mm and solder ball pitch of 0.4mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 °C have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (−40 to 125 °C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (≫ 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.

High-speed bend test method and failure prediction for drop impact reliability

The objective of this study is to obtain experimental failure models governing solder joint failure during drop impact testing of board assemblies. A high-speed bend test was developed to perform displacement-controlled bend test of board assemblies at the high flexing frequencies of drop impact. These test frequencies and amplitudes are not achievable by conventional universal testers. Experimental data was obtained for various PCB strain amplitudes, flexural frequencies solder alloys and pad finishes. Results from the high-speed bend tests are used to construct constant amplitude power law fatigue curves. Solder joint reliability found to be dependent on the test frequency, and therefore strain rate. The experimental failure data from these high-speed bend tests are a required basis for a drop impact failure criterion which can take into account frequency and amplitude effects and which is general enough to be applied to product level testing

Micro impact characterisation of solder joint for drop impact application

Good correlation has been established between high speed shearing of solder joint at component level and board level drop tests, endorsing high speed shearing as a viable quality assurance test for manufacturing and incoming inspection. The high speed shear characteristics of solder joints under different test conditions (shear speed, shear angle, and temperature) and aging conditions (multiple reflow, temperature humidity, and salt spray) have been evaluated. Preliminary S-N characteristic for SnPb_OSP and SnAg_OSP solder joints have been generated using high speed cyclic bends test. These could be devolved into a life prediction model for board level solder joints in product drop impact

Modeling Stress in Silicon With TSVs and Its Effect on Mobility

With the most popular electronic products being the slimmest ones with the highest functionality, the ability to thin, stack, and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3-D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5 × 10-6/°C) and silicon (2.5 × 10-6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this paper, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for: 1) designing substrates with TSVs such that mobility in the active devices are not affected by the presence of TSVs, and 2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

Underfill swelling and temperature-humidity performance of flip chip PBGA package

Two mechanisms for autoclave failure of flip chip PBGA packages have been identified. Transverse hygroscopic swelling of underfill has been found to be responsible for the first failure mechanism, typified by randomised solder joint failure associated with localised underfill-chip delamination around the solder joints. The localised delamination may coalesce into a larger delamination near the centre of the chip. In-plane hygroscopic swelling of underfill and substrate is responsible for the second failure mechanism. It results in extensive underfill-chip delamination initiating from the chip edge before solder joint failure. A vast difference in performance has been found for flip chip packages subjected to 85/spl deg/C/85%RH and 121/spl deg/C/100%RH conditioning, respectively. The compressive hygrothermal strain around the solder is believed to have contributed to the excellent performance during 85/spl deg/C/85%RH test.

Modelling stress in silicon with TSVs and its effect on mobility

With the most popular electronics products being the slimmest ones with the highest functionality, the ability to thin, stack and interconnect chips is becoming more important. One method to accomplish this is by using the through silicon via (TSV). This is a means of electrical connection in 3D stacked devices that saves space and shortens the electrical interconnect length, improving electrical performance [1]. Unfortunately, the large mismatch between the coefficients of thermal expansion (CTE) of copper (17.5×10−6/°C) and silicon (2.5×10−6/°C) has made the TSV a reliability concern. A mismatch in CTE translates to a mismatch in thermal strain when the wafer is subjected to large temperature loadings during fabrication [2, 3, 4]. This local thermal mismatch also induces stresses on the silicon surface around the vias which can affect the mobility of the silicon. In this study, the thermal stresses and strains induced on silicon due to the proximity of copper vias have been investigated for various geometries (via diameter, via pitch, silicon thickness, stacking layers) using finite element modeling. These results should be useful for (1) designing substrate with TSVs such that mobility in the active devices are not affected by the presence of TSVs and (2) understanding the limitations of stacking chips with respect to stress in silicon as well as joint reliability.

Low-Stress Bond Pad Design for Low-Temperature Solder Interconnections on Through-Silicon Vias (TSVs)

Low temperature bonds are thin intermetallic bonds that are formed between devices when plated layers of different metals on each side of the component come into contact under relatively low temperature and high pressure. These joints comprised completely of intermetallic compounds, will fail in a sudden unexpected manner, compared to normal solder joints which fail in a ductile manner where cracks grow more slowly. This problem of weak interconnects is further exacerbated when these thin interconnections are formed on pads located above through-silicon vias (TSVs). When a change in temperature occurs, the mismatch in coefficient of thermal expansion (CTE) causes the copper inside the TSV to expand or contract much more than the surrounding silicon. This could result in unexpectedly high tensile stresses in the joints. This additional tensile stress on post-formation cooling to room temperature increases the likelihood of joint failure. This paper presents a novel pad design to overcome the situation of high stress in the joints. The proposed design does not involve any additional fabrication or material cost. Simulation results show that with the proposed pad design, the maximum tensile stress in the interconnect decreases by 50%. Reliability assessment has also done in order to compare the proposed pad design with the conventional design. It is found that the samples with the proposed design have a better drop impact reliability performance and higher shear strength than the samples with the usual pad design.

Failure mechanisms of interconnections in drop impact

This study performs experimental tracking of crack propagation (stage II fatigue) in a single solder interconnection during drop impact. A high resolution, highspeed four-point resistance measurement system is used for tracking crack progression. Results indicate that most of the drop impact low-cycle fatigue life of the solder joint is spent in the crack initiation stage. Cross-sections and fractographs show that various mixes of intermetallic and bulk failure are possible within a single joint. Several failure mechanisms are suggested. Comparisons of failure modes are also made between drop impact, quasi-static loading and high-cycle fatigue. A thorough understanding of failure mechanisms is important for the development of failure criteria and life prediction models for drop impact