Ronald J. Bolam

Ring Oscillator Based Test Structure for NBTI Analysis

We have developed a new NBTI test structure comprising differential pairs of ring oscillators with stages of various circuit types. For stages consisting of inverters driving p-FET passgates, the gates of which are set at an adjustable DC potential, this structure allows high resolution absolute measurement of the average Vt shift of a large number (~ 100) product representative p-FETs in response to very short as well as traditional long duration pure NBTI AC or DC voltage/temperature stresses.

New breakdown data generation and analytics methodology to address BEOL and mol dielectric TDDB process development and technology qualification challenges

Both MOL PC-CA spacer dielectric and BEOL low-k dielectric breakdown data are commonly convoluted with multiple variables induced by process steps such as lithography, etch, CMP, cleaning, and thin film deposition. The traditional method of stressing one DUT per die or multiple DUTs per die, without careful data deconvolution, is incapable of addressing current complex MOL PC-CA and BEOL low-k dielectric breakdown modeling challenges. In this paper, a new big data generation method plus an analytics procedure method is proposed to soundly evaluate both MOL and BEOL dielectric time-dependent-dielectric breakdown data. A new diagnostic reliability concept is for the first time proposed for comprehensive process diagnostics and more accurate reliability failure rate determination.

A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS

A robust reliability characterization / modeling approach for accurately predicting Bias Temperature Instability (BTI) induced circuit performance degradation in High-k Metal Gate (HKMG) CMOS is presented. A series of device level stress experiments employing both AC and DC stress/relax BTI measurements are undertaken to characterize FETs threshold voltage instability response to a dynamic (inverter type) operation. Results from the AC stress experiments demonstrate that VT instability is frequency independent, an observation that suggests that VT degradation under AC stress can be equivalently measured through the simpler DC stress/relax sequence. An AC BTI model is developed that accurately captures the critical BTI relaxation effect through the DC stress/relax predictions on duty cycle dependence. A Ring Oscillator (RO) circuit is used as a model verification vehicle. Excellent agreement is demonstrated between the frequency degradation measurements obtained with a newly developed Ultra-Fast On-The-Fly (OTF) measurement technique optimized for BTI and the AC BTI model based RO simulations.

Nitrided gate oxides for 3.3-V logic application: reliability and device design considerations

Device characteristics and reliability in a 3.3-V logic CMOS technology with various gate oxidation and nitridation processes are described. The technology was designed to extend 3.3-V devices to the ultimate dielectric reliability limit while maintaining strict manufacturing cost control. A nitrided gate oxide provided the means to maintain hot-electron reliability at the level of the previous iteration, but at higher performance and lower processing cost. Conventional furnace processes in nitrous and nitric oxide, high-pressure oxidation in oxygen and nitrous oxide, and rapid-thermal processes using nitrous and nitric oxide were investigated. We found that the concomitant variations in fixed charge and thermal budget have a significant influence on both n-FET and p-FET device parameters such as threshold voltage, carrier mobility, and inverse short-channel effect (ISCE). Reliability effects, such as charge to breakdown (QBD), hot-electron degradation, and negative-bias temperature instability (NBTI) were examined and correlated with the nitrogen profile in the gate dielectric. Secondary ion mass spectroscopy (SIMS) profiles were used to characterize the oxidation techniques and to correlate gate dielectric composition to the parametric and reliability parameters.

Impact of shallow trench isolation on reliability of buried- and surface-channel sub-/spl mu/m PFET

Shallow trench isolation exhibits all the required isolation-technology properties for ULSI. Its high degree of scaleability relies on the fact that its lateral (isolation width) and vertical (isolation depth) dimensions are decoupled due to an almost-ideal box-shape profile of the isolation. A consequence of the abrupt device edge is that a parasitic drain-to-source leakage path can exist at the corner and along the trench sidewall. This paper describes degradation mechanisms of surface-channel (SC) and buried-channel (BC) PFET devices that are directly related with a corner and sidewall parasitic leakage. Both parasitic regions show a characteristic degradation behavior that can limit device reliability for PFETs in the sub-/spl mu/m regime. The necessary processing conditions that overcome this limitation are also given.

Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration

Abstract In these experiments, we explored various methods of nitridation of thermal oxide. Rapid thermal oxidation (RTO), rapid thermal oxidation with nitric oxide (RTNO), remote plasma nitridation (RPN), and decoupled plasma nitridation (DPN) processes were performed, and the result on 1.4, 2.2, and 5.2 nm oxides was measured. It is shown that the initial threshold voltage and the shift during negative bias temperature instability (NBTI) stress are proportional to the nitrogen in the oxide. Not surprisingly the threshold voltage is dependent on the interfacial nitrogen, but it was also found that the NBTI shift depends on the total nitrogen incorporated throughout the bulk of the insulator. The thinnest oxide showed boron penetration for the unnitrided split, but also very low NBTI shift. Furthermore, wafers from each of the aforementioned nitridation variants were processed with and without deuterium passivation. Although the NFET hot–carrier response is substantially improved, no significant advantage in NBTI shift is observed.

A thermally activated gate current in off-state PMOSFETs

Using buried-channel PFET devices with lightly doped drains (LDDs), the authors study the gate current and the threshold-voltage instability at intermediate electric fields and as a function of temperature. Although the same effects occur on surface-channel devices, larger potential differences were required because the built-in potential difference between N+ and P+ diffusions increases gate-induced diffusion leakage (GIDL) in buried-channel devices. Gate current was measured over a wide range of voltage and temperature on large gate perimeter PMOSFET devices. The measurements revealed a gate current with a voltage and temperature dependence proportional to the GIDL current. Hot electron stressing suggests the trapped charge is located near the gate-drain overlap region for short channel devices and near the intersection of the gate-drain overlap and the trench convex corner for narrow trench isolated devices.<<ETX>>

Dielectric step stress and life stress comparison

Voltage life-stress results have been compared with voltage step stress results. The figure of merit chosen for this comparison was TDDB. Two different oxides were used, one having a thickness of 13.5 nm and the other having a thickness of 8.2 nm.

Gate dielectric integrity and reliability in 0.5- mu m CMOS technology

Gate dielectric process and process-integration decisions involving the 0.5- mu m 16-Mb DRAM process for 200-mm wafers are discussed. Process-integration issues before, during, and after thin gate dielectric growth all affect the resulting dielectric reliability. Processes which are critical factors in gate dielectric integrity and reliability are discussed. IBMs 16-Mb DRAM CMOS technology employs shallow-trench isolation between the deep-trench storage capacitors. P-channel transfer devices are used and are connected to the deep-trench capacitors via a doped polysilicon surface strap. The gate dielectric is a 13-nm planar oxide and the transfer device channel lengths are 0.5 mu m. Gate dielectric yields were measured using long serpentine antenna test structures consisting of 128-kb cells in addition to segments of 16-Mb arrays. Dramatic gate dielectric reliability improvements have been achieved even with a starting point that was known to be less than optimal for the gate dielectric reliability. These improvements are graphically summarized.<<ETX>>

Applications of clustering model to bimodal distributions for dielectric breakdown

In this work, the authors report the extensive time-to-breakdown (TBD) data collected from back end of line/middle of the line and metal insulator metal capacitor dielectrics that exhibit not only non-Poisson area scaling but also multiple modal (or bimodal) breakdown characteristics. They develop a new bimodal modeling approach of the distributed competition process in conjunction with the time-dependent clustering model to extract the breakdown parameters and the characteristic breakdown time and slope (t63 and β) from this seemingly intractable breakdown data. While the number of parameters increases as a result of an increase in data complexity, these extracted parameters are consistent with Poisson area-scaling of fundamental weakest-link characteristics, and can thus be used for reliability projection. As a result, our modeling approach involving clustering model provides an important solution for technology qualification and dielectric-integrity assessment.