Surbhi Mittal

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge x Sb y Te z phase change material

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb2Te3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher Tx, thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

Gate-all-around silicon nanowire MOSFETs and circuits

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.

Optimization of programming current on endurance of phase change memory

We study the effect of programming current on the endurance failure of phase change memory and propose a general scheme of optimizing programming currents for the most endurance cycles. We consider two major endurance failure modes, stuck-SET and open failure. We show that higher current does not necessarily cause, and even prevents the earlier open failure and attribute it to phase-dependent open-failure mechanisms. As for the stuck-SET failure, RESET current is optimized to balance material segregation effect and RESET current margin. The overall programming conditions are optimized by combining open and stuck-SET failure characteristic curves.

Multiple double cross-section transmission electron microscope sample preparation of specific sub-10 nm diameter Si nanowire devices.

The ability to prepare multiple cross-section transmission electron microscope (XTEM) samples from one XTEM sample of specific sub-10 nm features was demonstrated. Sub-10 nm diameter Si nanowire (NW) devices were initially cross-sectioned using a dual-beam focused ion beam system in a direction running parallel to the device channel. From this XTEM sample, both low- and high-resolution transmission electron microscope (TEM) images were obtained from six separate, specific site Si NW devices. The XTEM sample was then re-sectioned in four separate locations in a direction perpendicular to the device channel: 90° from the original XTEM sample direction. Three of the four XTEM samples were successfully sectioned in the gate region of the device. From these three samples, low- and high-resolution TEM images of the Si NW were taken and measurements of the NW diameters were obtained. This technique demonstrated the ability to obtain high-resolution TEM images in directions 90° from one another of multiple, specific sub-10 nm features that were spaced 1.1 μm apart.

The impact of melting during reset operation on the reliability of phase change memory

Operation impact on endurance performance in GST-based phase change memory is investigated from small arrays to large test chips. SET operation induced electromigration and phase segregation are observed. For the first time, the RESET melting healing effect is proposed to partially repair the SET induced damage and further extend the endurance. This concept can be easily implemented by accordingly designing the control circuits.

Hybrid clean approach for post-copper CMP defect reduction

A “hybrid” post-Cu CMP cleaning process that combines acidic and basic cleans in sequence is developed and implemented. The new process demonstrates the advantages of both acidic and basic cleans and achieves a more than 60% reduction in CMP defects, such as polish residues, foreign materials, slurry abrasives, scratches, and hollow metal, relative to an all-basic brush clean process. It also eliminates the circular ring defects that occur intermittently during roller brush clean. TXRF scans confirm the reduction of AlOx defects when using the hybrid clean process. XPS spectra show similar Cu surface oxidation states between the basic and hybrid clean processes. Both short and open yields can be improved by using the new clean process. The underlying mechanism of the huge defect reduction benefits is discussed.

Interface state density measurements in gated p-i-n silicon nanowires as a function of the nanowire diameter

Gate-all-around p-i-n silicon nanowires (NW) diodes with effective nanowire diameter from 15 nm down to 4 nm (±1.3 nm) were fabricated to enable interface state density (Nit) measurements using the charge pumping (CP) method. The Nit of the NWs was also measured by the conductance method and was in good agreement with the CP method. The linear relation between the CP current and the pulse frequency was not maintained in the smallest diameter NWs. The dependency on the pulse rise and fall times was also investigated and is correlated to the lifetime of the traps. The impact of the cylindrical geometry on the measured CP current is discussed.

Multiple Double XTEM Sample Preparation of Sub-10 nm Diameter Si Nanowires

At Microscopy & Microanalysis 2009, we demonstrated that a transmission electron microscope (TEM) cross-section (X-TEM) sample of a specific, electrically tested sub-30 nm diameter Si nanowire (NW) semiconductor device could be prepared from a previously made X-TEM sample.[1] In this work, two physical measurements: the device gate length (from X-TEM sample 1) and NW diameter (from X-TEM sample 2 sectioned 90 from X-TEM 1) could be performed from the same electrically tested NW device. Here, the barrier where one or the other of these physical measurements had to be chosen to understand the electrical measurements of a specific device was broken. Now we will show how this initial technique is further extended to allow multiple X-TEM samples to be prepared from an existing X-TEM sample containing specific, electrically tested sub10 nm diameter Si NW devices.