Suketu A. Parikh

300mm copper low-k integration and reliability for 90 and 65 nm nodes

The paper addresses critical issues associated with 90 and 65 nm copper low k interconnects. A stable baseline with >98% yield on 1E7via and 5m long serpent was established. Electromigration (EM) and IV breakdown performance was improved by optimizing the post CMP Cu pre-treatment and the dielectric barrier obtaining EM T/sub 0.1/ lifetime of greater than 10 yrs at 1.5 MA/cm/sup 2/ and >6MV/cm IV breakdown field. Detailed characterization of the impact of the barrier process on stress migration (SM) is presented. Extendibility of the process flow to sub-90nm interconnects and advanced dielectric (k<2.7) is shown.

Influence of plating parameters on reliability of copper metallization

This work investigates the impact of plating parameters on the physical and electrical properties of plated copper films. Process parameters such as the plating current density and wafer rotation speed are known to affect the grain size and the residual stress in plated Cu films. We correlate the process parameters with trapped contamination in the films, which in turn influences the pre/post-anneal grain size and the relaxation of the residual stress. Preliminary reliability measurements show that the longevity of the interconnect structure is dependent on the intrinsic properties of the plated copper.

Characterization of electroless copper as a seed layer for sub-0.1 /spl mu/m interconnects

Complete gapfill of 0.1 /spl mu/m features with electroless Cu seed layers and electroplated Cu was demonstrated. Electrical tests on test structures indicated similar line and via chain resistance, yield and line-to-line leakage current on wafers with electroless Cu seed and PVD Cu seed layers filled with electroplated Cu.