Tetsu Ohtou

Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX

Characteristic variations of fully depleted silicon-on-insulator (SOI) MOSFETs with extremely thin buried oxide are examined by device simulations. It is found, for the first time, that a SOI device with low channel impurity concentration and high substrate concentration has high immunity to both parameter variations and random dopant fluctuations (RDFs). Fully depleted (FD) silicon-on-insulator (SOI) MOSFET, random dopant fluctuation (RDF), thin buried oxide (BOX), variability.

Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control

This paper describes a new device concept [a variable-body-factor fully depleted silicon-on-insulator (SOI) MOSFET], where the body factor is modulated by the substrate bias. The buried oxide in the SOI substrate is extremely thin. The operation principle, simulation result, measurement data of dc characteristics, and measurement data of ring oscillators are described, and the low-power/high-speed characteristics of this new device concept is discussed. It is also shown that the device concept is applicable to multiple-gate structures such as a FinFET.

Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme

The bias scheme of the variable body-factor fully depleted (FD) silicon-on-insulator (SOI) MOSFET, which has been previously proposed, is reexamined. Using a new scheme, the inversion and accumulation on the substrate in the active state can be avoided, and thus, ac performance in the active state is not degraded even with extremely thin buried-oxide (BOX), owing to the depletion of the substrate. Moreover, subthreshold leakage can be sufficiently suppressed in the standby state, owing to extremely thin BOX. This scheme provides threshold-voltage adjustability for the suppression of interdie and within-die variation in the active state. This device scheme is also applicable to multichannel FD SOI MOSFETs including FinFETs with a low-aspect-ratio fin, where the back-bias scheme can be applied

Variable Body Effect Factor Fully Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor for Ultra Low-Power Variable-Threshold-Voltage Complementary Metal Oxide Semiconductor Applications

We propose the concept of a variable body effect factor Fully Depleted Silicon-On-Insulator Metal Oxide Semiconductor Field Effect Transistor (FD SOI MOSFET) in which the body effect factor is varied by the substrate depletion capacitance. In this device, both higher drive current in the active mode and low leakage current in the standby mode can be obtained in the variable threshold voltage scheme. In the active mode, the body effect factor is reduced by the substrate depletion capacitance and the drive current increases. In the standby mode, the substrate is inverted or accumulated, and the depletion layer capacitance is neglected, resulting in a larger body effect factor that suppresses the standby subthreshold current. We demonstrate the validity of the proposed scheme with two-dimensional simulations and experiments.

Device design of nanoscale MOSFETs considering the suppression of short channel effects and characteristics variations

The device design of future nanoscale MOSFETs is reviewed. Major challenges in the design of the nanometer MOSFETs and the possible solutions are discussed. In this paper, special emphasis is placed on the combination of new transistor structures that suppress the short channel effect and on back-gate voltage control that suppresses the characteristics variations. Two new device architectures, variable-body-factor FD SOI MOSFET and multigate MOSFET with low aspect ratio, have been proposed and their advantages are discussed.

Short-Channel Characteristics of Variable-Body-Factor Fully-Depleted Silicon-On-Insulator Metal–Oxide–Semiconductor-Field-Effect-Transistors

The short-channel characteristics of variable-body-factor fully-depleted silicon-on-insulator (FD SOI) metal–oxide–semiconductor field-effect-transistors (MOSFETs), which we previously have proposed, are investigated by two-dimensional device simulation. It is found that, although the advantages of dc characteristics diminish in the short channel regime, improved ac characteristics can be obtained by the reduction in parasitic drain capacitance. The optimization of device parameters for variable-body-factor FD SOI MOSFETs is also discussed.

Low-power device design of fully-depleted SOI MOSFETs

A new device concept for variable /spl gamma/ FD (Fully-Depleted) SOI MOSFET is proposed by changing substrate depletion layer capacitance. Also a semi-planar 3D-gate SOI MOSFET is proposed, where both sufficient /spl gamma/ and good short effect immunity (SCE) is attained. These two device concepts are proposed for the future VLSI applications. The features of the proposed devices are: utilisation of substrate depletion layer below BOX (buried oxide), three-dimensional gate structure, and low aspect-ratio channel. The problems of standby power consumption, characteristic fluctuations, and performance degradation are solved. Three-dimensional simulation results of these devices are studied.

Experimental Demonstrations of Superior Characteristics of Variable Body-Factor (γ) Fully-Depleted SOI MOSFETs with Extremely Thin BOX of 10 nm

The superior characteristics of variable body-factor (γ) FD SOI MOSFETs which we have recently proposed are experimentally demonstrated. Devices were fabricated on a SOI wafer with BOX thickness of 10 nm by using the 140 nm technology. Their advantages, small leakage-current in the standby-state and improved delay in the active-state, are clearly validated by the measurements. This scheme is expected to be promising for future low-power, high-performance VLSIs

V/sub th/ control of t/sub pd/-degradation-free FD SOI MOSFET with extremely thin BOX using variable body-factor scheme

A new bias scheme of variable-/spl gamma/ FD SOI MOSFET is proposed. Using the scheme, almost no degradation of t/sub pd/ in the active-state is achieved even in the t/sub BOX/ of a sub-10 nm while I/sub off/ is sufficiently suppressed in the standby-state. Reducing the inter-die V/sub th/ fluctuation on a wide V/sub sub/ range in the active-state is realized. This device scheme is also well applicable to 3D channel MOSFETs including a FinFET.

Critical Substrate Bias in Variable Threshold Voltage CMOS (VTCMOS) Scheme with Short Channel Devices

where γ is the body factor and |ΔVbs| is the change in substrate bias. Eq. (1) shows that devices with larger γ value can achieve larger ΔVth, while it is also well known that devices with larger γ have smaller on-current due to a larger S factor and a smaller gm [2]. Hence, there is an apparent trade-off between Vth control and device performance. We have already discussed the trade-off of VTCMOS in the long channel regime and it is found that there exists the critical substrate voltage (V0) in VTCMOS [3]. It has been shown that devices with larger γ can achieve higher on-current when |ΔVbs| > V0. In VTCMOS, smaller V0 is preferable because we can take advantage of the effect of larger γ by utilizing only a small substrate bias. Therefore, V0 is one of the most important parameters. The physical origin of V0 has also been investigated and it has been found that V0 has two components: V0 = V01 + V02 [4]. In this paper, we investigate V0 of VTCMOS in the short channel regime for the first time based on ITRS 2004 hp90 LSTP [5]. We have also established models of V01 and V02 which are available in both long and short channel devices.