Y. Zhang

High-performance symmetric-gate and CMOS-compatible V/sub t/ asymmetric-gate FinFET devices

Double-gate FinFET devices with asymmetric and symmetric polysilicon gates have been fabricated. Symmetric gate devices show drain currents competitive with fully optimized bulk silicon technologies. Asymmetric-gate devices show |V/sub t/|/spl sim/0.1 V, with off-currents less than 100 nA/um at V/sub gs/=0.

Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs

A tensile-strained Si layer was transferred to form an ultra-thin (<20 nm) strained Si directly on insulator (SSDOI) structure. MOSFETs were fabricated, and for the first time, electron and hole mobility enhancements were demonstrated on strained Si directly on insulator structures with no SiGe layer present under the strained Si channel.

High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET I<inf>DSAT</inf> = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage V<inf>DD</inf> = 1 V and off-current I<inf>OFF</inf> = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed.

Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond

FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.

Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm

We demonstrate the worlds first top-down CMOS ring oscillators (ROs) fabricated with gate-all-around (GAA) silicon nanowire (NW) FETs having diameters as small as 3 nm. NW capacitance shows size dependence in good agreement with that of a cylindrical capacitor. AC characterization shows enhanced self-heating below 5 nm.

Low voltage, scalable nanocrystal flash memory fabricated by templated self assembly

We introduce a new method for building nanocrystal flash memory devices that achieves precise control of nanocrystal size and position. Nanocrystal dimensions are defined via polymer self assembly, facilitating device scaling. Devices exhibit low voltage memory operation with promising retention and endurance properties.

A Simplified Hybrid Orientation Technology (SHOT) for high performance CMOS

A new concept in high performance VLSI called Simplified Hybrid Orientation Technology (SHOT) is introduced. This novel process flow creates circuits with independently oriented surface channels for pMOS and nMOS by integrating FinFETs with planar Ultra-Thin SOI (UTSOI) MOSFETs for the first time. The unique CMOS structure enables high mobility surface channel orientation for both devices. The SHOT scheme is also capable of producing PDSOI devices on the same chip. pFinFET drive current is among the best results reported (810 /spl mu/A//spl mu/m at V/sub dd/ = 1.2V).

High performance FDSOI CMOS technology with metal gate and high-k

A high performance FDSOI CMOS technology featuring metal gate electrodes and high-k gate dielectrics is presented. Work-function tuning is accomplished by materials and process modification to achieve appropriate threshold voltages for FDSOI CMOS. The gate stacks exhibit an extremely thin effective inversion thickness (T/sub inv/) down to 14A with a gate leakage current of 0.2A/cm/sup 2/. This represents a six order of magnitude leakage reduction compared to Poly/SiO/sub 2/. By optimizing the gate stack, the highest unstrained electron mobility is realized (207cm/sup 2/A/s at E/sub eff/=1Mv/cm) at T/sub inv/=14A. Drive currents of 1050/spl mu/A//spl mu/m and 770/spl mu/A//spl mu/m at I/sub off/ of 90nA//spl mu/m and 28nA//spl mu/m are achieved for nMOS and pMOS respectively. This is the highest reported pFET drive current for metal gate transistors with high-k gate dielectrics. We also present FDSOI metal gate high-k ring oscillators and SRAM cells with static noise margin (SNM) of 328mV at V/sub dd/=1,2V.

Gate-all-around silicon nanowire MOSFETs and circuits

We demonstrate undoped-body, gate-all-around (GAA) Si nanowire (NW) MOSFETs with excellent electrostatic scaling. These NW devices, with a TaN/Hf-based gate stack, have high drive-current performance with NFET/PFET IDSAT = 825/950 µA/µm (circumference-normalized) or 2592/2985 µA/µm (diameter-normalized) at supply voltage VDD = 1 V and off-current IOFF = 15 nA/µm. Superior NW uniformity is obtained through the use of a combined hydrogen annealing and oxidation process. Clear scaling of short-channel effects versus NW size is observed. Additionally, we observe a divergence of the nanowire capacitance from the planar limit, as expected, as well as enhanced device self-heating for smaller diameter nanowires. We have also applied this method to making functional 25-stage ring oscillator circuits.

The micro to nano addressing block (MNAB)

Over the past few years, a number of techniques, including self-assembly, nanoimprint lithography and spacer-based frequency doubling, have been explored to pattern line and space structures that are considerably denser than possible with conventional photolithography, with excellent critical dimension control. In order to build useful circuits with them, an efficient way of interfacing these nanoscale lines with the photolithographically defined peripheral circuits is needed. While many solutions to this problem have been proposed, for the first time, we report a solution (MNAB) that is (a) fully silicon-process compatible, (b) non-stochastic (i.e. is completely deterministic,) and (c) does not require any critical alignment. The MNAB uses discrete analog potentials to deplete and switch off certain nanoscale lines enabling selection of the remaining nanoscale line. Simulation results show that individual nanoscale silicon lines can be addressed with selectivities (ratio of current in conducting line to that in depleted lines) exceeding 100times at features as small as 10 nm using this concept. Experimental results on various silicon prototypes show that selectivities exceeding 100times can be easily obtained even on sub-20 nm features